Logic control circuit

Claim 1

A control circuit for generating a series of pulses within a predetermined time interval in response to a command pulse preceeding said interval, comprising: a counter responsive to an applied signal for stepping from a reset state through a series of predetermined counting states including initial and final states, said counter comprising at least two counting elements, each element having first and second stable states, wherein said initial and final counting states of said counter correspond to first and second permutations in the stable states of said elements, and wherein one of said counting elements is in said first stable state only when said counter is in said reset and final counting states; a source of recurrent stepping pulses; means for applying said stepping pulses to said counter after said counter reaches said initial state to step said counter from said initial state to said final state; switch means, responsive to said elements existing in said second permutation, for interrupting the application of said stepping pulses to said counter when said counter assumes said final state, said switch means comprising a logical AND gate having an input coupled to said source of pulses and an output to the input of said counter, and having an additional input coupled to said second counting element to close said gate when said second counting element is in said first stable state; means for applying said command pulse to said counter to step said counter from said reset state to said initial counting state at the beginning of said predetermined time interval, comprising a logical OR gate having one input coupled to the source of said command pulse, another input coupled to the output of said logical AND gate, and an output coupled to the input of said counter; and means responsive to the counting state of said counter for generating said series of pulses as said counter advances from said initial state to said final state.