US3774052A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal detector circuit
Assignee: NCR Voyix Corp
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Filing: 1972-02-28
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Granted: 1973-11-20
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Expires: 1992-02-28
Abstract
Abstract There is disclosed a signal detector circuit for recognizing the presence of a sinusoidal input signal. The circuit includes complementary switching transistors for deenergizing first and second capacitors during respective positive and negative half cycles of the input signal. Further, first and second amplifying means are provided for providing signals which change respectively from positive to negative and negative to positive voltages as the two capacitors are discharged. A comparator provides an output signal when the two amplifier signals change polarity with respect to one another.
Inventors
- 👤 H Mcclain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H04; H04L; H04L1/00; H04L1/20
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
406 words
A detector circuit for providing an output signal indicating the presence of an established alternating current input signal applied thereto comprising: first and second capacitors for storing energy said first and second capacitors each having a first and a second terminal, said first terminals being coupled together and to a point of reference potential; input means for causing said first and said second capacitors to store an initial energy prior to the provision of said input signal and for periodically deenergizing said first capacitor during the occurrence of the positive half cycles of said input signal, and for periodically deenergizing said second capacitor during the occurrence of the negative half cylces of said input signal, said input means including first and second charging paths, each path including first and second series coupled resistive elements, said first charging path being coupled between a source of voltage of one polarity and said second terminal of said first capacitor, and said second charging path being coupled between a source of voltage of opposite polarity and said second terminal of said second capacitor; and wherein said input means further includes first and second switching means, said first switching means being coupled between the junction of said first and second resistive elements of said first charging path and said point of reference potential and passing current only during the positive half cycles of said input signal, said second switching means being coupled between the junction of said first and second resistive elements of said second charging path and said point of reference potential and passing current only during the negative half cycles of said input signal; first amplifying means responsive to the energy stored by said first capacitor for providing a signal which changes from a first to a second value as the energy stored by said first capacitor decreases; second amplifying means responsive to the energy stored by said second capacitor for providing a signal which changes from a third to a fourth value as the enerGy stored by said second capacitor decreases, said first and second amplifying means signals changing polarity with respect to one another as said energy stored by said first and second capacitors decreases, said first and fourth values being of one polarity and said second and third values being of another polarity; and comparing means for providing said output signal whenever said first and second amplifying means signals change polarity with respect to one another.
Claim 2
Dependent Claim
406 words
A detector circuit for providing an output signal indicating the presence of an established alternating current input signal applied thereto comprising: first and second capacitors for storing energy said first and second capacitors each having a first and a second terminal, said first terminals being coupled together and to a point of reference potential; input means for causing said first and said second capacitors to store an initial energy prior to the provision of said input signal and for periodically deenergizing said first capacitor during the occurrence of the positive half cycles of said input signal, and for periodically deenergizing said second capacitor during the occurrence of the negative half cylces of said input signal, said input means including first and second charging paths, each path including first and second series coupled resistive elements, said first charging path being coupled between a source of voltage of one polarity and said second terminal of said first capacitor, and said second charging path being coupled between a source of voltage of opposite polarity and said second terminal of said second capacitor; and wherein said input means further includes first and second switching means, said first switching means being coupled between the junction of said first and second resistive elements of said first charging path and said point of reference potential and passing current only during the positive half cycles of said input signal, said second switching means being coupled between the junction of said first and second resistive elements of said second charging path and said point of reference potential and passing current only during the negative half cycles of said input signal; first amplifying means responsive to the energy stored by said first capacitor for providing a signal which changes from a first to a second value as the energy stored by said first capacitor decreases; second amplifying means responsive to the energy stored by said second capacitor for providing a signal which changes from a third to a fourth value as the enerGy stored by said second capacitor decreases, said first and second amplifying means signals changing polarity with respect to one another as said energy stored by said first and second capacitors decreases, said first and fourth values being of one polarity and said second and third values being of another polarity; and comparing means for providing said output signal whenever said first and second amplifying means signals change polarity with respect to one another.
Claim 3
Dependent Claim
39 words
The invention according to claim 1 wherein said first and second switching means are first and second transistors respectively, said first transistor being rendered conductive by a positive voltage said second transistor being rendered conductive by a negative voltage.
Claim 4
Dependent Claim
95 words
The invention according to claim 2: wherein said first transistor is an N-P-N transistor having an emitter coupled to said point of reference potential, a collector coupled to said junction of said first and second resistive elements of said first charging path, and a base responsive to said input signal; and wherein said second transistor is a P-N-P transistor having an emitter coupled to said point of reference potential, a collector coupled to said junction of said first and second resistive elements of said second charging path, and a base responsive to said input signal.
Claim 5
Dependent Claim
258 words
The invention according to claim 1: wherein said first and second energy storing devices are first and second capacitors respectively; wherein said input means causes the voltage at one end of said first capacitor to initially assume a first voltage of one polarity and to be reduced in magnitude from said first voltage after said input signal occurs and further causes the voltage at one end of said second capacitor to initially assume a second voltage of the opposite polarity and to be reduced in magnitude from said second voltage after said input signal occurs; wherein said first amplifying means includes a first transistor having first and second main electrodes and a control electrode, means for coupling said first main electrode to a third voltage of said one polarity, means for coupling said second main electrode to a fourth voltage of said opposite polarity and means for coupling said control electrode to said one end of said first capacitor, said first amplifying means signal being the signal at said second main electrode of said first transistor; and wherein said second amplifying means includes a second transistor having first and second main electrodes and a control electrode, means for coupling said first main electrode to a fifth voltage of said opposite polarity, means for coupling said second main electrode to a sixth voltage of said one polarity and means for coupling said control electrode to said one end of said second capacitor, said second amplifying means signal being the signal at said second main electrode of said second transistor.
Claim 6
Dependent Claim
26 words
The invention according to claim 4 wherein said first and second voltages are respectively at least as large in magnitude as said third and fifth voltages.
Claim 7
Dependent Claim
14 words
The invention according to claim 5 wherein said comparing means includes a differential amplifier.
Claim 8
Dependent Claim
77 words
The invention according to claim 6: wherein said first transistor is a P-N-P transistor and said second transistor is an N-P-N transistor; wherein said first main electrodes of said first and second transistors are emitters, said second main electrodes of said first and second transistors are collectors and said control electrodes of said first and second transistors are bases; and wherein said means for coupling said first and second main electrodes to said voltages include resistive elements.
Claim 9
Dependent Claim
390 words
A detector circuit for providing an output signal after the occurrence of a predetermined number of cycles of an alternating current input signal comprising: first and second transistors of one conductivity, each having a collector, an emitter and a base; third and fourth tranSistors of opposite conductivity, each having a collector, an emitter and a base; first and second capacitor means, each having first and second terminals, said first terminals being coupled a point of reference potential; means for coupling said input signal to said bases of said first and third transistors; means for coupling the emitters of said first and third transistors to said point of reference potential; means, including a first resistor means, for coupling a source of voltage of a first polarity to the collector of said first transistor; means, including a second resistor means, for coupling a source of voltage of a second polarity to the collector of said second transistor, said first and second polarities being such that current can flow through said first and third transistors whenever said first and third transistors are rendered conductive by said input signal; means, including a third resistor means, for coupling the collector of said first transistor to the second terminal of said first capacitor; means, including a fourth resistor means, for coupling the collector of said third transistor to the second terminal of said second capacitor; means for coupling the second terminal of said first capacitor to the base of said fourth transistor; means for coupling the second terminal of said second capacitor to the base of said third transistor; means, including a fifth resistor means, for coupling the emitter of said fourth transistor to said source of voltage of said first polarity and, further including a sixth resistor means, for coupling the collector of said fourth transistor to said source of voltage of said second polarity; means, including a seventh resistor means, for coupling the emitter of said third transistor to said source of voltage of said second polarity and, further including an eighth resistor means, for coupling the collector of said third transistor to said source of voltage of said first polarity, and; differential amplifier means responsive to the voltages at the collectors of said second and fourth transistors, for providing said output signal whenever said collector voltages change polarities with respect to one another.
Claim 10
Dependent Claim
390 words
A detector circuit for providing an output signal after the occurrence of a predetermined number of cycles of an alternating current input signal comprising: first and second transistors of one conductivity, each having a collector, an emitter and a base; third and fourth tranSistors of opposite conductivity, each having a collector, an emitter and a base; first and second capacitor means, each having first and second terminals, said first terminals being coupled a point of reference potential; means for coupling said input signal to said bases of said first and third transistors; means for coupling the emitters of said first and third transistors to said point of reference potential; means, including a first resistor means, for coupling a source of voltage of a first polarity to the collector of said first transistor; means, including a second resistor means, for coupling a source of voltage of a second polarity to the collector of said second transistor, said first and second polarities being such that current can flow through said first and third transistors whenever said first and third transistors are rendered conductive by said input signal; means, including a third resistor means, for coupling the collector of said first transistor to the second terminal of said first capacitor; means, including a fourth resistor means, for coupling the collector of said third transistor to the second terminal of said second capacitor; means for coupling the second terminal of said first capacitor to the base of said fourth transistor; means for coupling the second terminal of said second capacitor to the base of said third transistor; means, including a fifth resistor means, for coupling the emitter of said fourth transistor to said source of voltage of said first polarity and, further including a sixth resistor means, for coupling the collector of said fourth transistor to said source of voltage of said second polarity; means, including a seventh resistor means, for coupling the emitter of said third transistor to said source of voltage of said second polarity and, further including an eighth resistor means, for coupling the collector of said third transistor to said source of voltage of said first polarity, and; differential amplifier means responsive to the voltages at the collectors of said second and fourth transistors, for providing said output signal whenever said collector voltages change polarities with respect to one another.
Claim 11
Dependent Claim
37 words
The invention according to claim 8: wherein said first and third transistors are N-P-N transistors and said second and fourth transistors are P-N-P transistors; and wherein said first polarity is positive and said second polarity is negative.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-19 | 1977-05-21 | 1977-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-19 | 1981-05-21 | 1981-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-19 | 1985-05-21 | 1985-11-20 | $7700.00 | Window Closed / Lapsed |