US3772663A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Status detector and memory arrangement
Assignee: AG Communication Systems Corp
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Filing: 1972-08-31
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Granted: 1973-11-13
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Expires: 1992-08-31
Abstract
Abstract Used in a stored program telephone switching system using a ring core memory in which word wires are connected at one end to a memory driver and at the other end to a memory switch which have memory input address leads, and a clock pulse input to each driver to actuate it to produce a current ramp. Peripheral units such as line circuits and junctors have relay contacts to indicate their status. The status detector comprises a pulse transformer having its secondary winding in series with an inductor connected at one end to an addressing gate, and at the other end to a lead to the status contacts, the other side of the status contacts being connected to a memory switch; so that when the gate and switch are both addressed and the status contacts path provides continuity the transformer is saturated. The primary of the transformer is connected to a memory driver and a sensing device such as a transformer or resistor, so that when the driver produces a current ramp pulse when the transformer is saturated an output is supplied from the sense device to a read amplifier associated with the ring core memory output.
Inventors
- 👤 D Shaver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:30
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54575; H04Q3/54591
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
355 words
A status detection arrangement in combination with a memory arrangement for a system having common control apparatus and a plurality of peripheral units; said memory arrangement comprising a plurality of ring-shaped magnetic cores with an individual sense winding on each core connected to read amplifier means, word wires selectively threaded through the inside of some cores and outside of others to thereby store information, memory input address means to select one of said word wires, and driver means to supply a current pulse to the selected word wire, to thereby generate an output pulse in the sense winding of each core having the selected wire threaded through it; said status detection arrangement comprising a status indicating switching means for each of said peripheral units, each of said status indicating switching means being connected to said memory input address means so that each peripheral unit has an individual address, and means responsive to coincidence of selection of the address of an individual peripheral unit having its status indicating switching means providing a continuity path from the memory input address means and actuation of said driver means to produce an output pulse to the read amplifier means; the improvement wherein said status detecting arrangement includes a pulse transformer having a primary winding and a secondary winding, with the secondary winding connected in series with the status indicating switching means to the memory input address means, and the primary winding connected to a driver means to supply a current pulse, and output means coupling the circuit path through the primary winding to said read amplifier means, the pulse transformer being saturated in response to the memory input address means selecting a peripheral unit having its said status indicating switching means closed to provide a continuity path, so that in response to a current pulse from said driver means with the pulse transformer saturated an output pulse is supplied to said read amplifier means, there being no significant output pulse produced when the pulse transformer does not have current flow through the secondary winding because the selected peripheral unit has an open path through its status indicating switching means.
Claim 2
Dependent Claim
355 words
A status detection arrangement in combination with a memory arrangement for a system having common control apparatus and a plurality of peripheral units; said memory arrangement comprising a plurality of ring-shaped magnetic cores with an individual sense winding on each core connected to read amplifier means, word wires selectively threaded through the inside of some cores and outside of others to thereby store information, memory input address means to select one of said word wires, and driver means to supply a current pulse to the selected word wire, to thereby generate an output pulse in the sense winding of each core having the selected wire threaded through it; said status detection arrangement comprising a status indicating switching means for each of said peripheral units, each of said status indicating switching means being connected to said memory input address means so that each peripheral unit has an individual address, and means responsive to coincidence of selection of the address of an individual peripheral unit having its status indicating switching means providing a continuity path from the memory input address means and actuation of said driver means to produce an output pulse to the read amplifier means; the improvement wherein said status detecting arrangement includes a pulse transformer having a primary winding and a secondary winding, with the secondary winding connected in series with the status indicating switching means to the memory input address means, and the primary winding connected to a driver means to supply a current pulse, and output means coupling the circuit path through the primary winding to said read amplifier means, the pulse transformer being saturated in response to the memory input address means selecting a peripheral unit having its said status indicating switching means closed to provide a continuity path, so that in response to a current pulse from said driver means with the pulse transformer saturated an output pulse is supplied to said read amplifier means, there being no significant output pulse produced when the pulse transformer does not have current flow through the secondary winding because the selected peripheral unit has an open path through its status indicating switching means.
Claim 3
Dependent Claim
21 words
The combination as claimed in claim 1, further including an inductor in series with the secondary winding of the pulse transformer.
Claim 4
Dependent Claim
31 words
The combination as claimed in claim 2, wherein said output means comprises a resistor in series with the primary winding, and a connection from the resistor to the read amplifier means.
Claim 5
Dependent Claim
39 words
The combination as claimed in claim 2, wherein said output means comprises an output transformer with a primary winding in series with the primary winding of the pulse transformer, and a secondary winding coupled to the read amplifier means.
Claim 6
Dependent Claim
186 words
The combination as claimed in claim 4, wherein said output transformer is common to a plurality of pulse transformers, with the primary winding of each pulse transformer connected in multiple to the primary winding of the output transformer; wherein said memory input address means supplies addresses with a first part and a second part, means coupled from the memory input address means to the secondary windings of the pulse transformers so that each pulse transformer has an individual address first part to select it, each primary winding being connected to a first side of a plurality of peripheral unit status indicating switching means, and switch means having inputs connected to the memory input address means and outputs to switch status leads so that each switch status lead has an individual address second part, each switch status lead being connected to a second side of a plurality of peripheral unit stAtus indicating switching means, each peripheral unit having said first and second sides of its status indicating switching means connected to be selected by its individual address comprising a combination of the first part and second part.
Claim 7
Dependent Claim
22 words
The combination as claimed in claim 5, wherein said status indicating switching means comprise relay contacts in series with isolation diode means.
Claim 8
Dependent Claim
130 words
The combination as claimed in claim 5, wherein the status detecting arrangement includes a plurality of said output transformers having their secondary windings coupled to different read amplifiers for respective bit positions of a word, with a set of pulse transformers connected to the primary winding of each output transformer, with the memory input address means coupled to the pulse transformers so that an address first part selects a pulse transformer in each set; and at least some of the peripheral units have a plurality of status indicating switching means with the first side connected individually to secondary windings of the pulse transformers having the same first part address in the respective sets, and the second side connected in common to the switch status lead for the address second part.
Claim 9
Dependent Claim
90 words
The combination as claimed in claim 7, wherein the memory input address means is coupled to said memory arrangement so that an address first part selects a first end of a plurality of word wires to effectively couple them to driver means; and wherein said switch means for the address second part is common to the status detection arrangement and the memory arrangement, with second ends of word wires connected thereto so that a word wire is selected by an individual combination of an address first part and second part.
Claim 10
Dependent Claim
59 words
The combination as claimed in claim 8, wherein the connections from the memory input address means to the status detection arrangement and the memory arrangement provides for the addresses of at least some peripheral units to select both its status indicating switching means and a word wire of the memory arrangement, with different bit positions of an output word.
Claim 11
Dependent Claim
303 words
A status detecting arrangement for a system having an address register and a plurality of peripheral units with status indicating switching means, with two sets of output leads from the address register for a first part and a second part of addresses respectively; said status detecting arrangement comprising a pulse transformer having a primary winding and a secondary winding, an inductor in series with the secondary winding, a gate having input connections to the set of leads for the address first part and an output having a first potential when enabled by its address input connections, the series combination of the inductor and primary winding being connected between the output of the gate and a first side of the status indicating switching means of a plurality of peripheral units, a plurality of switch means having input connections to the set of leads for the address second part and each having an output lead having a second potential when enabled by its address input connections, the status indicating switching means of each peripheral unit having a second side connected to the output of one switch means, the pulse transformer being saturated responsive to an address from the address register enabling the gate and switch means of a peripheral unit having a closed path via its status indicating switching means, and not saturated for other addresses; driver means connected to the primary winding to supply a current pulse when enabled by a clock pulse, and output means coupled to the primary winding circuit path, the pulse transformer having low impedance in the primary winding circuit path when saturated, so that a current pulse from the driver means produces an output pulse at said output means, there being no significant output pulse produced when the pulse transformer is not saturated because it then has high impedance.
Claim 12
Dependent Claim
303 words
A status detecting arrangement for a system having an address register and a plurality of peripheral units with status indicating switching means, with two sets of output leads from the address register for a first part and a second part of addresses respectively; said status detecting arrangement comprising a pulse transformer having a primary winding and a secondary winding, an inductor in series with the secondary winding, a gate having input connections to the set of leads for the address first part and an output having a first potential when enabled by its address input connections, the series combination of the inductor and primary winding being connected between the output of the gate and a first side of the status indicating switching means of a plurality of peripheral units, a plurality of switch means having input connections to the set of leads for the address second part and each having an output lead having a second potential when enabled by its address input connections, the status indicating switching means of each peripheral unit having a second side connected to the output of one switch means, the pulse transformer being saturated responsive to an address from the address register enabling the gate and switch means of a peripheral unit having a closed path via its status indicating switching means, and not saturated for other addresses; driver means connected to the primary winding to supply a current pulse when enabled by a clock pulse, and output means coupled to the primary winding circuit path, the pulse transformer having low impedance in the primary winding circuit path when saturated, so that a current pulse from the driver means produces an output pulse at said output means, there being no significant output pulse produced when the pulse transformer is not saturated because it then has high impedance.
Claim 13
Dependent Claim
85 words
A status detecting arrangement as claimed in clAim 10, wherein said output means is coupled in common to the primary winding circuit paths of a plurality of pulse transformers, each of the pulse transformers having its secondary winding connected in series with an individual inductor to an individual gate, the gates being enabled by different address first parts, the secondary windings of the pulse transformers being connected to the first sides of the status indicating switching means of different pluralities of peripheral units forming groups.
References Cited (Backward Citations)
US3529092A
Cited
US3587070A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-12 | 1977-05-14 | 1977-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-12 | 1981-05-14 | 1981-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-12 | 1985-05-14 | 1985-11-13 | $7700.00 | Window Closed / Lapsed |