US3772600A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital bit synchronizer
Assignee: United States Department of the Air Force
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Filing: 1972-07-14
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Granted: 1973-11-13
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Expires: 1992-07-14
Abstract
Abstract A system for deriving synchronizing pulses from a train of digital signals that is fed to in-phase and mid-phase gates each including an adder with a delay feedback. The output of the midphase gate is multiplied by a sign factor determined by a logic circuit connected to the in-phase gate. The output of the two gates are then mixed, filtered, and summed with a value dependent upon the clock rate and fed to a number controlled oscillator which includes a counter and a comparing circuit. The output of the number controlled oscillator is fed back to the in-phase and mid-phase gates.
Inventors
- 👤 F Natali
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:26
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0332; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
241 words
A system for deriving synchronizing pulses from a train of digital signals comprising: a. a clock; b. an in-phase gate the timing thereof being controlled by the clock including 1. a first adder fed by the train of digital signals, and 2. a first register connecting the output of the first adder to the input in a feedback loop; c. a multiplying logic circuit fed by the in-phase gate, the multiplying factor being dependent upon the sum within the inphase gate; d. a mid-phase gate the timing thereof being controlled by the clock including 1. a second adder fed by the train of digital signals, and 2. a second register connecting the output of the second adder to the input in a feedback loop; e. a mixer fed by the logic circuit and the mid-phase gate; f. a filter fed by the mixer; g. a summing circuit fed by the filter and a signal the value thereof being equal to the ratio of the time length of a digital signal to the pulse period of the clock; h. a counter fed by the clock; i. a first comparing circuit fed by the counter and the summing circuit, the output of the first comparing circuit being fed to the counter as a reset pulse; and j. a second comparing circuit fed by the counter and the summing circuit, the output of the second comparing circuit being fed to the multiplying logic circuit.
Claim 2
Independent Claim
241 words
A system for deriving synchronizing pulses from a train of digital signals comprising: a. a clock; b. an in-phase gate the timing thereof being controlled by the clock including 1. a first adder fed by the train of digital signals, and 2. a first register connecting the output of the first adder to the input in a feedback loop; c. a multiplying logic circuit fed by the in-phase gate, the multiplying factor being dependent upon the sum within the inphase gate; d. a mid-phase gate the timing thereof being controlled by the clock including 1. a second adder fed by the train of digital signals, and 2. a second register connecting the output of the second adder to the input in a feedback loop; e. a mixer fed by the logic circuit and the mid-phase gate; f. a filter fed by the mixer; g. a summing circuit fed by the filter and a signal the value thereof being equal to the ratio of the time length of a digital signal to the pulse period of the clock; h. a counter fed by the clock; i. a first comparing circuit fed by the counter and the summing circuit, the output of the first comparing circuit being fed to the counter as a reset pulse; and j. a second comparing circuit fed by the counter and the summing circuit, the output of the second comparing circuit being fed to the multiplying logic circuit.
Claim 3
Dependent Claim
52 words
a first register connecting the output of the first adder to the input in a feedback loop; c. a multiplying logic circuit fed by the in-phase gate, the multiplying factor being dependent upon the sum within the in-phase gate; d. a mid-phase gate the timing thereof being controlled by the clock including
Claim 4
Dependent Claim
52 words
a first register connecting the output of the first adder to the input in a feedback loop; c. a multiplying logic circuit fed by the in-phase gate, the multiplying factor being dependent upon the sum within the in-phase gate; d. a mid-phase gate the timing thereof being controlled by the clock including
Claim 5
Dependent Claim
134 words
a second register connecting the output of the second adder to the input in a feedback loop; e. a mixer fed by the logic circuit and the mid-phase gate; f. a filter fed by the mixer; g. a summing circuit fed by the filter and a signal the value thereof being equal to the ratio of the time length of a digital signal to the pulse period of the clock; h. a counter fed by the clock; i. a first comparing circuit fed by the counter and the summing circuit, the output of the first comparing circuit being fed to the counter as a reset pulse; and j. a second comparing circuit fed by the counter and the summing circuit, the output of the second comparing circuit being fed to the multiplying logic circuit.
Claim 6
Dependent Claim
134 words
a second register connecting the output of the second adder to the input in a feedback loop; e. a mixer fed by the logic circuit and the mid-phase gate; f. a filter fed by the mixer; g. a summing circuit fed by the filter and a signal the value thereof being equal to the ratio of the time length of a digital signal to the pulse period of the clock; h. a counter fed by the clock; i. a first comparing circuit fed by the counter and the summing circuit, the output of the first comparing circuit being fed to the counter as a reset pulse; and j. a second comparing circuit fed by the counter and the summing circuit, the output of the second comparing circuit being fed to the multiplying logic circuit.
Claim 7
Dependent Claim
88 words
A system for deriving synchronizing pulses according to claim 1 wherein the multiplying logic circuit includes: a. a first flip-flop having complementary inputs and outputs, the inputs being fed by the in-phase gate; b. a second flip-flop fed by the complementary outputs of the first flip-flop; c. a first inverting gate fed by one output Of each of the first and second flip-flops; and d. a second inverting gate fed by the opposite outputs of the first and second flip-flops from that fed to the first inverting gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-12 | 1977-05-14 | 1977-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-12 | 1981-05-14 | 1981-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-12 | 1985-05-14 | 1985-11-13 | $7700.00 | Window Closed / Lapsed |