Error correction for self-synchronized scramblers

Claim 2

In a data transmission system in which information sequences are encoded in a BCH code which can correct t errors, where t is an integer, said code being generated by means of a polynomial whose roots are Alpha i where i 1, 3, . . . 2t-1, scrambled for transmission through a digital channel, and descrambled after transmission to recover said code, a method of correcting errors introduced by said channel which are changed into multiple error patterns by said descrambler comprising the steps of: generating electrical signals representing remainder polynomial

Claim 3

In a system for decoding code words of a double-error-correcting BCH code including random errors which have been unavoidably multiplied into randomly occurring predetermined error patterns, apparatus comprising: first means for successively dividing the code words by the polynomial g1(x) x4 + x + l to obtain a first remainder r1(x) indicative of the predetermined error patterns; second means for successively dividing the code words by the polynomial g3(x) x4 + x3 + x2 + x + 1 to obtain a second remainder r3(x) indicative of the predetermined error patterns; third means for linearly transforming r1(x) into a first syndrome component S1 that contains information for locating each random error that caused each predetermined error pattern; fourth means for linearly transforming r3(x) into a second syndrome component S3 that contains information for locating each random error that caused each predetermined error pattern; fifth means for generating correction signals from the syndrome components S1 and S3; and sixth means for combining each correction signal from the output of said fifth means with the code words at a plurality of error locations corresponding to each predetermined error pattern to produce an output signal from said sixth means free of errors.

Claim 4

In a system for decoding code words of a double-error-correcting BCH code including random errors which have been unavoidably multiplied into randomly occurring predetermined error patterns, apparatus comprising: first means for successively dividing the code words by the polynomial g1(x) x4 + x + l to obtain a first remainder r1(x) indicative of the predetermined error patterns; second means for successively dividing the code words by the polynomial g3(x) x4 + x3 + x2 + x + 1 to obtain a second remainder r3(x) indicative of the predetermined error patterns; third means for linearly transforming r1(x) into a first syndrome component S1 that contains information for locating each random error that caused each predetermined error pattern; fourth means for linearly transforming r3(x) into a second syndrome component S3 that contains information for locating each random error that caused each predetermined error pattern; fifth means for generating correction signals from the syndrome components S1 and S3; and sixth means for combining each correction signal from the output of said fifth means with the code words at a plurality of error locations corresponding to each predetermined error pattern to produce an output signal from said sixth means free of errors.

Claim 5

The apparatus of claim 2 wherein said sixth means for combining comprises first and second adding means each having one input terminal connected to output of said fifth means, delaying means connected from the output terminal of said first adding means to the other input terminal of said second adding means, the other input terminal of said first adding means being connected to receive the code words, and said first and second adding means combIning the correction signals and the code words to eliminate the error patterns from the output of said second adding means.

Claim 6

The apparatus of claim 2 further comprising: means for checking the parity of each code word to determine the overall parity weight of each code word, means for inverting the first information bit of each code word when the output of said parity checking means indicates odd parity weight, means for modifying the S1 and S3 output signals of said third and fourth means when the output of said means for checking parity indicates odd parity weight, and said means for modifying cancelling that portion of S1 and S3 signals indicative of the first information bit before inversion.

Claim 7

The apparatus of claim 4 wherein said sixth means comprise first, second and third adding means each having two input terminals and an output terminal; first delaying means connected from the output terminal of said first adding means to an input terminal of said second adding means, second delaying means connected from the output terminal of said second adding means to the input terminal of said third adding means, switching means connected from the output of said fifth means to an input terminal of said first and third adding means, said second adding means having an input terminal connected to the output of said fifth means, and said switching means completing the signal path from either said fifth means to said first adding means or said third adding means, the signal path from said fifth means to said third adding means being completed when the last information bit in the code word is passing through said second adding means.

Claim 8

The apparatus of claim 3 wherein said delaying means has an interval such that when one information bit in the code word is passing through said second adding means the next successive information bit is passing through said first adding means.

Claim 9

The apparatus of claim 5 wherein said first delaying means has a delay interval substantially equal to the time interval between successive information bits in the code word, and said second delaying means has a delay interval substantially equal to the time interval between the first and last information bits in the code word.