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US3770984A Expired / Lapsed US ⏱️ 0.0 years remaining

Fast recovery low distortion limiter circuit

Assignee: Harris Corp
•
Filing: 1971-03-03
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Granted: 1973-11-06
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Expires: 1991-03-03
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Abstract

Abstract A signal limiter for reducing and increasing the gain of a circuit with the required speed of response without introducing distortion in the limiter output. The limiter includes a variable gain circuit having an output coupled to a detector in a feedback loop. The detector develops a DC signal which is then coupled back to the gain control device to reduce or increase the gain in accordance with the output signal level. A charging circuit is coupled to a point between the detector and the gain controlling device to hold a high level signal appearing at the output of the detector for a given time interval. Switching means are then provided to discharge the charging circuit after the lapse of a predetermined time interval to allow the gain to return to normal. This assures that the gain of the gain controlling device will not fluctuate in response to every signal waveform peak. Such rapid fluctuations would result in distortion at the output of the limiter. The switching circuit consists of several forms. One of the forms comprises a transistor having a second charging circuit coupled to the emitter thereof. The discharge time of the second charging circuit allows the transistor to be turned on to discharge the main charging circuit and allow the gain of the gain controlling device to return to normal. In a second form, the second charging circuit is coupled to the base of the transistor, and the operation is similar to that described above. In a further embodiment, a switching means of any general configuration may be provided in shunt with the main charging circuit and operated according to a given timing sequence. In another embodiment, a zener diode may be used to discharge the principal charging circuit when the voltage applied to the anode thereof through a second charging circuit decreases to a given level.

Inventors

  • 👤 D Connor
  • 👤 Donough R Mc

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 19:15
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3005; H03G11/00

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 230 words
A signal limiter comprising: a gain controlling means, a detector coupled to an output of said controlling means for developing a DC signal therefrom, means coupling an Output of said detector to an input of said gain controlling device for regulating the gain thereof when a relatively high level signal is developed at the output of said detector, means for holding said input of said gain controlling device at a relatively high level for a given time interval after the lapse of said relatively high level signal at the output of said detector, means for reducing the signal level at the input of said gain controlling device after the lapse of said given time interval when the output of said detector is at a relatively low signal level, said means for reducing the signal level at the input of said gain controlling device after the lapse of said given time interval including a switching device coupled in parallel with said means for holding said input of said gain controlling device at a relatively high level, means for opening and closing the switching device at predetermined time intervals, said means for opening and closing the switching device at predetermined time intervals including a charging and discharging circuit for building up a charge at high signal levels and for discharging according to said given time interval, said switching device being zener diode.
Claim 2
Dependent Claim 230 words
A signal limiter comprising: a gain controlling means, a detector coupled to an output of said controlling means for developing a DC signal therefrom, means coupling an Output of said detector to an input of said gain controlling device for regulating the gain thereof when a relatively high level signal is developed at the output of said detector, means for holding said input of said gain controlling device at a relatively high level for a given time interval after the lapse of said relatively high level signal at the output of said detector, means for reducing the signal level at the input of said gain controlling device after the lapse of said given time interval when the output of said detector is at a relatively low signal level, said means for reducing the signal level at the input of said gain controlling device after the lapse of said given time interval including a switching device coupled in parallel with said means for holding said input of said gain controlling device at a relatively high level, means for opening and closing the switching device at predetermined time intervals, said means for opening and closing the switching device at predetermined time intervals including a charging and discharging circuit for building up a charge at high signal levels and for discharging according to said given time interval, said switching device being zener diode.
Claim 3
Dependent Claim 174 words
A signal limiter comprising: a gain controlling means, a detector coupled to an output of said gain controlling means for developing a DC signal therefrom, means coupling an output of said detector to an input of said gain controlling device for regulating the gain thereof when a relatively high level signal is developed at the output of said detector, a point of reference potential, a control circuit coupled from the input of the gain controlling device to the point of reference potential, said control circuit including the parallel combination of a capacitor and transistor, said capacitor holding said input of said gain controlling device at a relatively high level for a given time interval after the lapse of said relatively high level signal at the output of said detector, control means for turning on said transistor to discharge said capacitor after the lapse of said given time interval when the output of said detector is at a relatively low signal level, and said transistor having a conduction path in series with said control means.
Claim 4
Dependent Claim 174 words
A signal limiter comprising: a gain controlling means, a detector coupled to an output of said gain controlling means for developing a DC signal therefrom, means coupling an output of said detector to an input of said gain controlling device for regulating the gain thereof when a relatively high level signal is developed at the output of said detector, a point of reference potential, a control circuit coupled from the input of the gain controlling device to the point of reference potential, said control circuit including the parallel combination of a capacitor and transistor, said capacitor holding said input of said gain controlling device at a relatively high level for a given time interval after the lapse of said relatively high level signal at the output of said detector, control means for turning on said transistor to discharge said capacitor after the lapse of said given time interval when the output of said detector is at a relatively low signal level, and said transistor having a conduction path in series with said control means.
Claim 5
Dependent Claim 41 words
A signal limiter in accordance with claim 2 wherein said control means for turning on said transistor comprises a charging and discharging circuit for building up a charge at high signal levels and for discharging according to said given time interval.
Claim 6
Dependent Claim 31 words
A signal limiter in accordance with claim 3 wherein said charging and discharging circuit is coupled to one of the terminals of said transistor for controlling the conduction or non-conduction thereof.
Claim 7
Dependent Claim 22 words
A signal limiter in accordance with claim 4 wherein said charging and discharging circuit is coupled to the emitter of said transistor.
Claim 8
Dependent Claim 22 words
A signal limiter in accordance with claim 4 wherein said charging and discharging circuit is coupled to the base of said transistor.

References Cited (Backward Citations)

US2957074A Cited
US3021489A Cited
US3050692A Cited
US3109989A Cited
US3441866A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-11-05 1977-05-07 1977-11-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-11-05 1981-05-07 1981-11-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-11-05 1985-05-07 1985-11-06 $7700.00 Window Closed / Lapsed

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