Time division switching system bridging circuit

Claim 2

In a time division communication system having a plurality of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit for exchanging signals among two or more selected communication path storage devices comprising a first common bus, a second common bus, means for defining a fIrst group of time slots in each repetitive cycle, means for assigning one selected communication path storage device to each first group time slot, means for associating one selected communication path storage device with each second group time slot, a first storage device selectively connectible to said second common bus, apparatus operative in each of said first group of time slots comprising means for sampling the signal in the storage device assigned to the occuring first group time slot and for applying said sample signal to said first common bus, means responsive to said sampled signal on said first common bus for generating and applying a first signal corresponding to said assigned storage device sampled signal to said first storage device via said second bus whereby said first storage device stores the sum of the assigned storage device sampled signals at the end of said first group of time slots, apparatus operative in each of said second group of time slots comprising means for sampling the signal in the storage device associated with the occurring second group time slot and for applying said associated storage device sampled signal to said first common bus, means for sampling the sum signal in said first storage device and for applying said sampled sum signal to said second common bus, and means connected to said first and second common buses for generating and applying a second signal corresponding to the difference between the sampled sum signal and twice the associated storage device sampled signal to said associated storage device whereby each associated storage device receives the sum of the sampled signals from the other associated storage devices.

Claim 3

In a time division communication system having a plurality of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 1 further comprising means operative during the last time slot of said second group of time slots for removing the stored sum signal from said first storage device.

Claim 4

In a time division communication system having a plurality of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 2 wherein said first signal generating and applying means comprises means for producing a first pulse having a duration corresponding to said assigned storage device sampled signal, and means responsive to said produced first pulse for generating and applying a first constant current signal to said first storage device via said second common bus, and said second signal generating and applying means comprises means for producing a second pulse having a duration corresponding to the difference between said sampled sum signal and twice said associated storage device sampled signal, and means responsive to said produced second pulse for generating and applying a second constant current signal to said associated storage device.

Claim 5

In a time division communication system having a plurality of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 3 wherein said first pulse producing means comprises means for producing a pulse having a duration proportional to the magnitude of said first signal, said first constant current generating means comprises means for generating a constant current signal of the same polarity as said assigned storage device sampled signal and having the same duration as said produced first pulse; and said second pulse producing means comprises means for producing a pulse having a duration proportional to the magnitude of the difference between said sampled sum signal and twice said associated storage device sampled signal, and said second constant current generating and applying means comprises means for generating a constant current signal of the same polarity as said difference signal and having the same duration as said produced second pulse.

Claim 6

In a time division communication sYstem having a plurality of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 4 wherein each of said communication path storage devices comprises a storage capacitor and said first storage device comprises a first storage capacitor.

Claim 7

In a time division communication system having a plurality of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 5 wherein said stored sum signal removing means comprises means operative during the last time slot of said second group of time slots for discharging said first storage capacitor.

Claim 8

In a time division communication system having first and second groups of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit for bridging two or more selected first group communication path storage devices in each repetitive cycle comprising a first common bus, a second common bus, means for defining a first plurality of time slots and a second plurality of time slots in each repetitive cycle, means for assigning a selected first group communication path storage device to each of the first plurality of time slots, means for associating one selected first group communication path storage device with each of the second plurality of time slots in each repetitive cycle, a bridging storage device selectively connectible to said second common bus, apparatus operative in each of said first plurality of time slots comprising means for sampling the signal in the storage device assigned to the occuring one of said first plurality of time slots and for applying said assigned storage device sample signal to said first common bus, means responsive to said assigned storage device sampled signal on said first common bus for generating and applying a first signal corresponding to said assigned storage device sampled signal to said bridging storage device via said second bus whereby said bridging storage device stores the sum of the selected storage device sampled signals at the end of said first plurality of time slots, apparatus operative in each of said second plurality of time slots comprising means for sampling the signal in the storage device associated with the occurring one of said second plurality of time slots and for applying said associated storage device sampled signal to said first common bus, means for sampling the sum signal in said bridging storage device and for applying said sampled sum signal to said second common bus, means connected to said first and second common buses for generating and applying a second signal corresponding to the difference between the sampled sum signal and twice the associated storage device sampled signal to said associated storage device whereby each associated storage device receives the sum of the sampled signals from the other associated storage devices.

Claim 9

In a time division communication system having first and second groups of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit for bridging two or more selected first group communication path storage devices in each repetitive cycle comprising a first common bus, a second common bus, means for defining a first plurality of time slots and a second plurality of time slots in each repetitive cycle, means for assigning a selected first group communication path storage device to each of the first plurality of time slots, means for associating one selected first group communication path storage device with each of the second plurality of time slots in each repetitive cycle, a bridging storage device selectively connectible to said second common bus, apparatus operative in each of said first plurality of time slots comprising means for sampling the signal in the storage device assigned to the occuring one of said first plurality of time slots and for applying said assigned storage device sample signal to said first common bus, means responsive to said assigned storage device sampled signal on said first common bus for generating and applying a first signal corresponding to said assigned storage device sampled signal to said bridging storage device via said second bus whereby said bridging storage device stores the sum of the selected storage device sampled signals at the end of said first plurality of time slots, apparatus operative in each of said second plurality of time slots comprising means for sampling the signal in the storage device associated with the occurring one of said second plurality of time slots and for applying said associated storage device sampled signal to said first common bus, means for sampling the sum signal in said bridging storage device and for applying said sampled sum signal to said second common bus, means connected to said first and second common buses for generating and applying a second signal corresponding to the difference between the sampled sum signal and twice the associated storage device sampled signal to said associated storage device whereby each associated storage device receives the sum of the sampled signals from the other associated storage devices.

Claim 10

In a time division communication system having first and second groups of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 7 further comprising means operative in the last time slot of said second plurality of time slots for removing the stored sum signal from said bridging storage device.

Claim 11

In a time division communication system having first and second groups of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 8 wherein said first signal generating and applying means comprises means for producing a first pulse having a duration corresponding to said assigned storage device sampled signal, means responsive to said produced first pulse for generating and applying a first constant current signal of the same polarity as said assigned storage device sampled signal to said bridging storage device via said second common bus, and said second signal generating and applying means comprises means for producing A second pulse having a duration corresponding to the difference between said sampled sum signal and twice said associated storage device sampled signal, and means responsive to said produced second pulse for generating and applying a second constant current signal of the same polarity as said difference to said associated storage device.

Claim 12

In a time division communication system having first and second groups of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 9 wherein said first pulse producing means comprises means for producing a pulse having a duration proportional to the magnitude of said first signal, said first constant current generating means comprising means making the duration of said constant current signal the same as said produced first pulse, and said second pulse producing means comprises means for producing a pulse having a duration proportional to the magnitude of the difference between said sampled sum signal and twice said associated storage device sampled signal, and said constant current generating and applying means comprises means for making the duration of the second constant current signal the same as said produced second pulse.

Claim 13

In a time division communication system having first and second groups of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 10 wherein each of said communication path storage devices comprises a storage capacitor and said bridging storage device comprises a bridging storage capacitor.

Claim 14

In a time division communication system having first and second groups of communication path storage devices wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 11 wherein said stored sum signal removing means comprises normally open switching means connected to said bridging capacitor, said normally open switching means being operative in the the last time slot of said second plurality of time slots for discharging the sum signal in said bridging storage capacitor.