US3767855A
Expired / Lapsed
US
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Pulse position modulation communication system
Assignee: NEC Corp
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Filing: 1972-02-22
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Granted: 1973-10-23
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Expires: 1992-02-22
Abstract
Abstract A pulse position modulation communication system which elminates the need for generating independent synchronizing pulses at transmitter facility. Numerical data is generated sequentially and is temporarily stored. The next occurring data is summed with the previously stored data, and the sum is transmitted in a position within a time frame representative of the numerical value. Simultaneously therewith this resultant sum replaces the previously stored data for summation with the next received data. Addition is performed by a modulo-M summing operation (i.e., ignoring any carry) where the value of M is the same as the number of time slots in each time frame. Subtraction of received pulse position data is performed in a similar manner at the receiver to restore the data to its original form.
Inventors
- 👤 Y Ueno
- 👤 M Kajitani
- 👤 Y Takimoto
- 👤 T Shinoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:19
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0066; H04B; H04B14/00; H04B14/02; H04B14/026
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
302 words
A transmitter employing pulse position modulation techniques wherein no independent synchronizing pulses are required, comprising; input means for sequentially receiving one group of signals at a time wherein each group of signals is comprised of n digital signals representing a numerical value, where n is a real integer; means coupled to said input means for temporarily storing the last received group of signals; timing means having first and second outputs, said first output coupled to said storing means for transferring said group of signals from said input means to said storing means at a predetermined time; binary counter means coupled to said timing means second output for generating a binary output representative of a numerical value, said counter means having n stages, each stage being associated with one of said n digital signals; coincidence circuit means coupled to said storing means and said counter means for generating an output when coincidence occurs between a digital signal state in one of said stages and its associated signal in said group; inhibitor means coupled to said coincidence circuit means and said timing means for producing at least one pulse for each favorablE coincidence comparison within one of a predetermined number of positions within a time frame and for inhibiting the generation of any additional pulses within the same time frame wherein the position of said produced pulse represents the numerical value of the digital signal in said group of digital signals associated therewith, and wherein each binary signal of a predetermined digital value present in said group of digital signals is generated in a different time frame, said time frames being of equal time duration; delay means coupled between said inhibitor means and said counter means for resetting said counter means before the occurrence of the next group of pulses at said input means.
Claim 2
Dependent Claim
302 words
A transmitter employing pulse position modulation techniques wherein no independent synchronizing pulses are required, comprising; input means for sequentially receiving one group of signals at a time wherein each group of signals is comprised of n digital signals representing a numerical value, where n is a real integer; means coupled to said input means for temporarily storing the last received group of signals; timing means having first and second outputs, said first output coupled to said storing means for transferring said group of signals from said input means to said storing means at a predetermined time; binary counter means coupled to said timing means second output for generating a binary output representative of a numerical value, said counter means having n stages, each stage being associated with one of said n digital signals; coincidence circuit means coupled to said storing means and said counter means for generating an output when coincidence occurs between a digital signal state in one of said stages and its associated signal in said group; inhibitor means coupled to said coincidence circuit means and said timing means for producing at least one pulse for each favorablE coincidence comparison within one of a predetermined number of positions within a time frame and for inhibiting the generation of any additional pulses within the same time frame wherein the position of said produced pulse represents the numerical value of the digital signal in said group of digital signals associated therewith, and wherein each binary signal of a predetermined digital value present in said group of digital signals is generated in a different time frame, said time frames being of equal time duration; delay means coupled between said inhibitor means and said counter means for resetting said counter means before the occurrence of the next group of pulses at said input means.
Claim 3
Dependent Claim
29 words
The transmitter of claim 1 wherein the pulse rate of pulses appearing at said second output is greater than the pulse rate of pulses appearing at said first output.
Claim 4
Dependent Claim
45 words
The transmitter of claim 1 wherein the counter means is adapted to generate a maximum count of M, where M is a real integer equal to or greater than 2 and wherein M is equal to the number of time slots in each time frame.
Claim 5
Dependent Claim
235 words
A receiver utilizing pulse position modulation techniques comprising: input means for receiving a series of pulses, each pulse occurring within a different time frame wherein all time frames are of equal length and wherein the position of a pulse in its time frame represents a predetermined numerical value; clock means coupled to said input means for generating timing signals; counter means coupled to said input means being reset upon receipt of a pulse from said input means; said counter means being coupled to said clock means for generating signals representing a binary count after having been reset; memory means coupled to said input means and said counter means for storing the contents of said counter means upon the occurrence of the next signal at said input means; word synchronizing means coupled to said clock means for generating a narrow pulse representing the beginning of each time frame when the total number of pulse positions in a time frame has been detected; means coupled to said memory means and said word synrhconizing means for receiving the contents of said memory upon the initiation of the next time frame and only during the occurrence of the pulse from said word synchronizing means representing the initiation of the next time frame delay means coupled between said input means and said counter means for resetting said counter means a predetermined time after application of pulses upon said input means.
Claim 6
Dependent Claim
235 words
A receiver utilizing pulse position modulation techniques comprising: input means for receiving a series of pulses, each pulse occurring within a different time frame wherein all time frames are of equal length and wherein the position of a pulse in its time frame represents a predetermined numerical value; clock means coupled to said input means for generating timing signals; counter means coupled to said input means being reset upon receipt of a pulse from said input means; said counter means being coupled to said clock means for generating signals representing a binary count after having been reset; memory means coupled to said input means and said counter means for storing the contents of said counter means upon the occurrence of the next signal at said input means; word synchronizing means coupled to said clock means for generating a narrow pulse representing the beginning of each time frame when the total number of pulse positions in a time frame has been detected; means coupled to said memory means and said word synrhconizing means for receiving the contents of said memory upon the initiation of the next time frame and only during the occurrence of the pulse from said word synchronizing means representing the initiation of the next time frame delay means coupled between said input means and said counter means for resetting said counter means a predetermined time after application of pulses upon said input means.
Claim 7
Dependent Claim
35 words
The receiver of claim 4 wherein the said word synchronizing circuit generates a narrow pulse after developing a count of M, where M is equal to the number of time slots in a time frame.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |