Converter for segment companded pcm codes

Claim 2

A digital converter for directly converting an input signal encoded in accordance with a first segment companding law to an output signal encoded in accordance with a second segment companding law, wherein each code comprises a first group of m characteristic digits e1e2 - - em defining the segment L and a second group of n mantissa digits e1e2 - - en defining the quantizing step V in the segment, said converter comprising a source of clock pulses t for producing a counting cycle and means for performing on the input signal L1V1, under control of the clock pulses, the algorithm W(z) z 2 U(z) where z is an operator representing multiplication by two and one clock interval delay, xi L1-L2 where L1 is the segment term of the input signal and L2 is the segment term of the output signal, W(z) represents the converted signal, Eta 2 0 when L1 0 and 1 when L1 NOT = 0, and U(z) is given by (zV1(z) + z5-z5 L + 1-z L ) where V1(z) is the mantissa term of the input signal, said means for performing the algorithm comprising a binary counter and a first AND gate having one inhibited input for generating the second term (z5 L ), a shift register for generating the first term (zV1(z) + z5), subtractor means for subtracting the second term from the first term to produce U(z), means for applying U(z) to a serial input of said shift register, and means for monitoring the output of said binary counter and the serial input of said shift register to produce a shift in U(z) in accordance with the shift operator z 2, said last mentioned means further inhibiting the counting of said binary counter by the term xi to produce, at the last count of the cycle of said source of clock pulses (L2 L1- xi ) in said counter, and means for extracting the converted signal L2V2 from said counter and shift register.

Claim 3

A digital converter as claimed in claim 1 wherein the means for monitoring comprises a first OR gate having applied thereto the output of said first AND gate and the output of said subtractor means, a second ANd gate having an inverted input to which the output of said first OR gate is applied and an input supplied with a pulse at time period T5 from a first pulse generator controlled by said source of clock pulses, a third AND gate for controlling the shifting of said shift register having one input supplied with pulses from said source of clock pulses and an inverted input supplied with the output from said second AND gate for inhibiting the said shift register from shifting when said second AND gate produces a pulse on its output.

Claim 4

A digital converter as claimed in claim 2 wherein the means for monitoring further comprises a fourth AND gate for producing an output only when said binary counter output is 110, the output of said fourth AND gate being applied to one input of a second OR gate, the other input of said second OR gate being an inverted input having the output of a second pulse generator under control of said source of clock pulses applied thereto at time period T6, the output Of said second OR gate being applied to a third input of said third AND gate.

Claim 5

A digital converter as claimed in claim 2 and further including an AND gate having one input connected to said source of clock pulses and its output connected to said binary counter for controlling the counter and an inverted input connected to the output of said third AND gate for halting the counting of said counter upon the occurrence of a pulse output from said third AND gate.

Claim 6

A digital converter for directly converting an input signal encoded in accordance with a first segment companding law to an output signal encoded in accordance with a second companding law, wherein each code comprises a first group of m characteristic digits e1e2 - - em defining the segment L and a second group of n mantissa digits e1e2 - - en defining the quantizing step V in the segment, said converter comprising an m cell binary counter to which the characteristic digits are applied in parallel, a shift register having n + 2 cells to which the characteristic digits are applied in parallel, a source of clock pulses for producing a timing cycle of t1t2 -- t8 pulses, the periods between pulses representing time periods T1T2 - - T8, means for applying the clock pulses to said binary counter to cause it to count for a predetermined number of pulses, a first AND gate having m inputs, at least one of which is inverted, each input being connected to one cell of said binary counter, said first AND gate producing an output upon the occurrence of the time pulse whose number in the cycle corresponds to five minus the original entry in said binary counter, means including a second AND gate for applying clock pulses to said shift register to cause it to produce a sequential pulse output, subtracting means having one input connected to the output of said first AND gate and a second input connected to the output of said shift register for subtracting the output of said first AND gate from the output of said shift register, means for feeding back the output of said subtracting means to a sequential input of said shift register, means for inhibiting the shifting of said shift register for one time period comprising a first OR gate having inputs connected to the outputs of said first AND gate and said subtracting means and its output connected to an inverted input of a third AND gate, means for enabling said third AND gate only during the time period T5, the output of said third AND gate being connected to an inverted input of said second AND gate whereby said shift register is prevented from shifting when said first OR gate produces no output during time period T5, means for inhibiting the action of said counter comprising a fourth AND gate having an inverted output connected to the output of said third AND gate whereby the counter is inhibited for one count when said first OR gate produces no output during the time period T5, and means for extracting in parallel the digital information in said counter and said shift register at the completion of the timing cycle.

Claim 7

A digital converter for directly converting an input signal encoded in accordance with a first segment companding law to an output signal encoded in accordance with a second companding law, wherein each code comprises a first group of m characteristic digits e1e2 - - em defining the segment L and a second group of n mantissa digits e1e2 - - en defining the quantizing step V in the segment, said converter comprising an m cell binary counter to which the characteristic digits are applied in parallel, a shift register having n + 2 cells to which the characteristic digits are applied in parallel, a source of clock pulses for producing a timing cycle of t1t2 -- t8 pulses, the periods between pulses representing time periods T1T2 - - T8, means for applying the clock pulses to said binary counter to cause it to count for a predetermined number of pulses, a first AND gate having m inputs, at least one of which is inverted, each input being connected to one cell of said binary counter, said first AND gate producing an output upon the occurrence of the time pulse whose number in the cycle corresponds to five minus the original entry in said binary counter, means including a second AND gate for applying clock pulses to said shift register to cause it to produce a sequential pulse output, subtracting means having one input connected to the output of said first AND gate and a second input connected to the output of said shift register for subtracting the output of said first AND gate from the output of said shift register, means for feeding back the output of said subtracting means to a sequential input of said shift register, means for inhibiting the shifting of said shift register for one time period comprising a first OR gate having inputs connected to the outputs of said first AND gate and said subtracting means and its output connected to an inverted input of a third AND gate, means for enabling said third AND gate only during the time period T5, the output of said third AND gate being connected to an inverted input of said second AND gate whereby said shift register is prevented from shifting when said first OR gate produces no output during time period T5, means for inhibiting the action of said counter comprising a fourth AND gate having an inverted output connected to the output of said third AND gate whereby the counter is inhibited for one count when said first OR gate produces no output during the time period T5, and means for extracting in parallel the digital information in said counter and said shift register at the completion of the timing cycle.

Claim 8

A digital converter as claimed in claim 5 and further including means for inhibiting the shifting of said shift register during the time period T6 comprising a fifth AND gate having an input connected to each cell of said counter, at least one input being inverted, said fifth AND gate producing an output only when the output of said counter is 110, a second OR gate having one input connected to the output of said fifth AND gate and an inverted input connected to a pulse source under control of said source of clock pulses, which produces a pulse at time period T6, the output of said second OR gate being connected to an input of said second AND gate whereby said shift register is inhibited from shifting when the output of said binary counter is other than 110 during time period T6.