Current divider

Claim 2

A current divider comprising current terminals carrying currents having predetermined integral ratios relative to one another, said ratios differing from unity between at least two currents of said current terminals, a common terminal carrying the sum of the currents at said current terminals, a plurality of circuits for connecting each of said current terminals to said common sum terminal, said circuits comprising at least one semiconductor element in each circuit for producing the currents at said terminals, said semiconductor elements comprising transistors of the same type having equal base-emitter voltages thereby passing emitter currents of said ratios, the highest common factor being unity current, at least one of said semiconductor elements operating as a diode, and compensating circuits for correcting deviations in said ratios caused by the base currents of the transistors of said circuits corresponding to said emitter current, said compensating circuits comprising at least one transistor having its emitter-collector path in a circuit having a current deviation of one polarity and its base connected to a circuit having a current deviation of opposite polarity, said compensating transistor having the same ratios between the base and emitter currents as the transistors of said circuits.

Claim 3

Current divider as claimed in claim 1, wherein one of the current terminals comprises an input terminal for receiving an input current, the circuit connecting the input terminal to the common sum terminal being the input circuit, and the remaining current terminals comprise output terminals, the circuits connecting the output terminals to the common sum terminals being output circuits, said compensating circuits operating so that a connection between the input terminal and the sum terminal comprises only base-emitter paths of the transistors of said circuits and any connections between the output terminals and the sum terminal comprises the collector of at least one transistor.

Claim 4

Current divider as claimed in claim 2, wherein the compensating circuit comprises a plurality of diodes so that at least the base-emitter paths of the transistors, shunted by a base-emitter path of another transistor, have minimum collector-base voltages.

Claim 5

Current divider as claimed in claim 2, wherein one output terminal carries a current that is n times the current supplied to said input terminal, the sum terminal being connected to the emitters of (n + 1) matched transistors having parallel-connected base-emitter paths, one of said (n + 1) matched transistors being connected in said input circuit and the remaining transistors being connected in said output circuits, one of the n transistors in said output circuit operating as a diode and being connected to the output terminal through the emitter-collector path of a first compensating transistor, the collectors of the remaining transistors in the output circuits being connected to the output terminal, and the base of said compensating transistor being connected to the collector of the input circuit transistor and the input terminal.

Claim 6

Current divider as claimed in claim 2, comprising an output terminal carrying a current that is 1/n times the current at said input terminal, said sum terminal being connected to the emitters of (n+1) matched transistors having parallel-connected base-emitter paths, one of said (n+1) transistors being connected in said output circuit and the remaining transistors being connected in said input circuit, two of the transistors connected in the input circuit operating as diodes and being connected through the emitter-collector path of a second compensating transistor to the input terminal, the collectors of the remaining transistors in the input circuit being connected to the input terminal, the base of said second compensating transistor being connected between the collector of the transistor in the output circuit and the emitter of a first compensating transistor having its base connected to the input terminal and its collector connected to the output terminal.

Claim 7

Current divider as claimed in claim 2, comprising an output terminal carrying a current that is n/(n + 1) times the input current at said input terminal, said sum terminal being connected to the emitters of (n + n + 1) matched transistors having parallel-connected base-emitter paths, (n + 1) of these transistors being connected in the input circuit and the remaining n transistors being connected in the output circuits, the collectors of the n transistors in the input circuit being connected to the input terminal, the transistors in the output circuit operating as diodes and having their common collector connected through the series connection of the emitter-collector paths of first and third compensating transistors to the output terminal, the base of the first compensating transistor being connected to the collectors of the remaining input circuit transistors and through the emitter collector path of a second compensating transistor to the input terminal, the base of the second compensating transistor being connected between the emitter of the third compensating transistor and the collector of the first compensating transistor and the base of the third compensating transistor being connected to the input terminal.

Claim 8

Current divider as claimed in claim 2, wherein said plurality of circuits comprises a first and a second output circuit, and said current terminals comprise a first and a second output terminal, the currents at the input terminal and at the first and at the second output terminal being in a ratio of 1 : n : (n + 1), the sum terminal being connected to the emitters of (1 + n + n + 1) matched transistors having parallel-connected base-emitter paths, one of said (1 + n + n + 1) transistors being in the input circuit, n of said (1 + n + n + 1) transistors being in the first output circuit and the remaining (n + 1) transistors being in the second output circuit, the (n + 1) transistors in the second output circuit being connected as diodes and having their common collector connected through the emitter-collector path of a first compensating transistor to the second output terminal, the collectors of (n - 1) transistors in the first output circuit being connected to the first output terminal, and the collector of the remaining transistors in the first output circuit being connected to the base of the first compensating transistor and, through the emitter-collector path of a second compensating transiStor to the first output terminal, the base of the said second compensating transistor being connected to the collector of the transistor in the input circuit and the input terminal.

Claim 9

Current divider as claimed in claim 2, wherein said plurality of circuits comprise p output circuits and said current terminals comprise p output terminals, the currents at the input terminals and at the output terminals being in the ratio of 1 : 1 : 2 : 4 . . . 2p 1, the sum terminal being connected to the emitters of (1 + 1 + 2 + 4 . . . . + 2p 1) matched transistors having parallel-connected base-emitter paths, each circuit comprising a plurality of said transistors corresponding to said ratios, the 2p 1 transistors in the pth output circuit operating as diodes and each output circuit comprising the emitter-collector paths of compensating transistors connecting the interconnected collectors of the transistors in respective output circuits to respective output terminals, the base of each compensation transistor being connected to the collectors of the transistors in the preceding circuits.

Claim 10

Current divider as claimed in claim 2, wherein said plurality of circuits comprises 4 output circuits and said current terminals comprise 4 output terminals, the currents at the input terminal and at the 4 output terminals being in the ratio of 1 : 1 : 2 : 2 : 4, the sum terminal being connected to the emitter of (1 + 1 + 2 + 2 + 4) matched transistors having parallel-connected base-emitter paths, each circuit comprising a plurality of these transistors which corresponds to said ratio, the four transistors in the fourth output circuit operating as diodes and having their interconnected collectors connected through the series connection of the emitter-collector path of a first and a third compensating transistor to the fourth output terminal, the base of the first compensating transistor being connected to the interconnected collectors of the transistors included in the third output circuit and through the emitter-collector path of a second compensating transistor to the third output terminal, the base of the third compensating transistor being connected to the interconnected collectors of the transistors in the second output circuit and through the emitter-collector path of a fourth compensating transistor to the second output terminal, the base of this fourth compensating transistor being connected to the collector of the transistor included in the first output circuit and through the emitter-collector path of a fifth compensating transistor to the first output terminal, the base of this fifth compensating transistor being connected to the input terminal and to the collector of the transistor included in the input circuit, and the base of the second compensating transistor being connected between the collector of the first compensating transistor and the emitter of the third compensating transistor.

Claim 11

Current divider as claimed in claim 2, wherein said plurality of circuits comprises two output circuits and said current terminals comprise a first and a second output terminal, the input currents at the input terminal being in the ratio of 1 : 1 : 2, the sum terminal being connected to the emitters of a first and a second matched transistor, the base-emitter paths of said transistors being connected in parallel, the first transistor operating a diode and being connected through the emitter-collector path of a first compensating transistor to the second output terminal, the collector of the second transistor being connected to the emitters of a third and a fourth matched transistor having parallel-connected base-emitter paths, said third transistor operating as a diode and being connected to the first output terminal, and the fourth transistor being connected to the input terminal and to the base of the compensating transistor.

Claim 12

Current divider comprisiNg the cascade arrangement of a plurality of current dividers as claimed in claim 10, wherein each output circuit comprises the emitter-collector path of an additional compensating transistor having its emitter connected to the base of the additional compensating transistor in the succeeding output circuit, the base of the additional compensating transistor in the first output circuit being connected to the input terminal, and the emitter of the additional compensating transistor in the last output circuit being connected to the base of an additional compensating transistor having its collector connected to the sum terminal thereby deriving the sum current from the emitter of said additional compensating transistor.

Claim 13

A digital to analogue converter comprising means for producing digital signals, a current divider for receiving output currents representing the digital signals, said current divider comprising current terminals carrying currents having integral ratios of 1 : 1 : 2 : 4 . . . . 2p 1, a common terminal carrying the sum of the currents at said current terminals, one of said current terminals comprising an input terminal for receiving input currents, the circuit connecting the input terminal to the common sum terminal being the input circuit, and the remaining current terminals comprising output terminals, the circuits connecting the output terminals to the common sum terminals being output circuits, a plurality of circuits for connecting each of p output terminals to said common sum terminal, said circuits comprising at least one transistor in each circuit for producing the currents at said terminals, said transistors being of the same type and having equal base-emitter voltages thereby passing emitter currents having said ratios, the common sum terminal being connected to the emitters of (1 + 1 + 2 + 4 . . . +2p 1) matched transistors having parallel-connected base-emitter paths, each circuit comprising a plurality of said transistors corresponding to said ratios, the 2p 1 transistors in the pth output circuit operating as diodes, and compensating transistors for correcting deviations in said ratios caused by the base currents of the transistors of said circuit corresponding to said emitter current, said compensating transistor comprising at least one transistor having its emitter-collector path in a circuit having a current deviation of one polarity and the base of said compensating transistor in a circuit having a current deviation of opposite polarity said compensating transistors having the same ratios between the base and emitter currents as the transistors of said circuits and operating so that connections between the input terminal and the sum terminal comprises only base-emitter paths of the transistors of said circuits and any connections between the output terminals and the sum terminal comprises the collector of at least one transistor, and means for operating with said current divider to produce an output voltage corresponding to the sum of said currents corresponding to the digital signal.

Claim 14

A digital to analogue converter comprising means for producing digital signals, a current divider for receiving output currents representing the digital signals, said current divider comprising current terminals carrying currents having integral ratios of 1 : 1 : 2 : 4 . . . . 2p 1, a common terminal carrying the sum of the currents at said current terminals, one of said current terminals comprising an input terminal for receiving input currents, the circuit connecting the input terminal to the common sum terminal being the input circuit, and the remaining current terminals comprising output terminals, the circuits connecting the output terminals to the common sum terminals being output circuits, a plurality of circuits for connecting each of p output terminals to said common sum terminal, said circuits comprising at least one transistor in each circuit for producing the currents at said terminals, said transistors being of the same type and having equal base-emitter voltages thereby passing emitter currents having said ratios, the common sum terminal being connected to the emitters of (1 + 1 + 2 + 4 . . . +2p 1) matched transistors having parallel-connected base-emitter paths, each circuit comprising a plurality of said transistors corresponding to said ratios, the 2p 1 transistors in the pth output circuit operating as diodes, and compensating transistors for correcting deviations in said ratios caused by the base currents of the transistors of said circuit corresponding to said emitter current, said compensating transistor comprising at least one transistor having its emitter-collector path in a circuit having a current deviation of one polarity and the base of said compensating transistor in a circuit having a current deviation of opposite polarity said compensating transistors having the same ratios between the base and emitter currents as the transistors of said circuits and operating so that connections between the input terminal and the sum terminal comprises only base-emitter paths of the transistors of said circuits and any connections between the output terminals and the sum terminal comprises the collector of at least one transistor, and means for operating with said current divider to produce an output voltage corresponding to the sum of said currents corresponding to the digital signal.

Claim 15

An adjustable current source comprising a current divider, said divider comprising current terminals carrying currents having predetermined integral ratios relative to one another, a common terminal carrying the sum of the currents at said current terminal, one of said current terminals comprising an input terminal, the circuit connecting the input terminal to the common sum terminal being the input circuit, and the remaining current terminals comprising output terminals, the circuits connecting the output terminals to the common sum terminals being output circuits, a plurality of circuits for connecting each of said current terminals to said common sum terminal, said circuits comprising at least one semiconductor element in each circuit for producing the currents at said terminals, said semiconductor elements comprising transistors of the same type having equal base-emitter voltages Thereby passing emitter currents of said ratios, the highest common factor being unity current, at least one of said semiconductor elements operating as a diode, and compensating circuits for correcting deviations in said ratios caused by the base currents of the transistors of said circuits corresponding to said emitter current, said compensating circuits comprising at least one transistor having its emitter-collector path in a circuit having a current deviation of one polarity and its base connected to a circuit having a current deviation of opposite polarity, said compensating transistor having the same ratios between the base and emitter currents as the transistors of said circuits, a circuit arrangement comprising first and second circuits terminating in a common sum terminal, said input and output terminals of said current divider being connected to said second and first circuits respectively, said first circuit comprising transistors of a type opposite to the transistors of said current divider and having its emitter connected to said common sum terminal, and means for compensating for current deviations cause by the base current of said transistor, said second circuit comprising a transistor of the same type as the transistor of said first circuit and operating as a diode, and a variable resistor in series and shunting the base-emitter path of the transistor of said first circuit.

Claim 16

An adjustable current source comprising a current divider, said divider comprising current terminals carrying currents having predetermined integral ratios relative to one another, a common terminal carrying the sum of the currents at said current terminal, one of said current terminals comprising an input terminal, the circuit connecting the input terminal to the common sum terminal being the input circuit, and the remaining current terminals comprising output terminals, the circuits connecting the output terminals to the common sum terminals being output circuits, a plurality of circuits for connecting each of said current terminals to said common sum terminal, said circuits comprising at least one semiconductor element in each circuit for producing the currents at said terminals, said semiconductor elements comprising transistors of the same type having equal base-emitter voltages Thereby passing emitter currents of said ratios, the highest common factor being unity current, at least one of said semiconductor elements operating as a diode, and compensating circuits for correcting deviations in said ratios caused by the base currents of the transistors of said circuits corresponding to said emitter current, said compensating circuits comprising at least one transistor having its emitter-collector path in a circuit having a current deviation of one polarity and its base connected to a circuit having a current deviation of opposite polarity, said compensating transistor having the same ratios between the base and emitter currents as the transistors of said circuits, a circuit arrangement comprising first and second circuits terminating in a common sum terminal, said input and output terminals of said current divider being connected to said second and first circuits respectively, said first circuit comprising transistors of a type opposite to the transistors of said current divider and having its emitter connected to said common sum terminal, and means for compensating for current deviations cause by the base current of said transistor, said second circuit comprising a transistor of the same type as the transistor of said first circuit and operating as a diode, and a variable resistor in series and shunting the base-emitter path of the transistor of said first circuit.

Claim 17

Current divider as claimed in claim 10, wherein each output circuit comprises the emitter-collector path of an additional compensating transistor having its emitter connected to the base of said additional compensating transistor in the succeeding output circuit, the base of the additional compensating transistor in the first output circuit being connected to the input terminal, and the emitter of the additional compensating transistor in the last output circuit being connected to the base of an additional compensating transistor having its collector connected to the sum terminal thereby deriving the sum current from the emitter of said additional compensating transistor.

Claim 18

A digital to analogue converter as claimed in claim 12, wherein said plurality of circuits comprises two output circuits and said current terminals comprise a first and a second output terminal, the input current at the input terminal and the output currents at the first and second output terminals being in the ratio of 1 : 1 : 2, the sum terminal being connected to the emitters of a first and a second matched transistor, the base-emitter paths of said transistors being connected in parallel, the first transistor operating as a diode and being connected through the emitter-collector path of a first compensating transistor to the second output terminal, the collector of the second transistor being connected to the emitters of a third and a fourth matched transistor having parallel-connected base-emitter paths, said third transistor operating as a diode and being connected to the first output terminal, the fourth transistor being connected to the input terminal and to the base of the compensating transistor.

Claim 19

A digital to analogue converter comprising the cascade arrangement of a plurality of current dividers as claimed in claim 15, wherein each output circuit comprises the emitter-collector path of an additional compensating transistor having its emitter connected to the base of the additional compensating transistor in the succeeding output circuit, the base of the additional compensating transistor in the first output circuit being connected to the input terminal, and the emitter of the additional compensating transistor in the last output circuit being connected to the base of an additional compensating transistor having its collector connected to the sum terminal thereby deriving the sum current from the emitter of said additional compensating transistor.