US3766448A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated igfet circuits with increased inversion voltage under metallization runs
Assignee: Arris Technology Inc
•
Filing: 1972-02-04
•
Granted: 1973-10-16
•
Expires: 1992-02-04
Abstract
Abstract Inversion voltage in selected regions in an integrated array is increased by changing the geometry of the metallization overlying the thick oxide in the selected region. More particularly, metallization runs extending over functionally unrelated diffused regions in a semiconductor substrate are divided into a plurality of narrow stripes in the area between said unrelated diffused regions, whereby the subsequent alloying process is ineffective to ''''anneal out'''' the surface states or trapped charge at the substrate-oxide interface, thereby leaving a high inversion voltage at that region of the substrate so as to prevent unwanted channelling.
Inventors
- 👤 R Luce
- 👤 E Schlegel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:44
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10D; H10D99/00; Y; Y10; Y10S; Y10S438/00; Y10S438/91
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
122 words
In a semiconductor integrated circuit array comprising a semiconductor substrate, an insulating layer disposed over said substrate, a plurality of semiconductor devices integrated on said substrate and operatively electrically connected by a plurality of conductive stripes disposed on said insulating layer, said conductive stripes comprising an active metal alloyed at an elevated temperature on said insulating layer, the improvement comprising a selected region of at least one of said stripes being divided into a plurality of narrower stripes electrically connected in parallel defining a multisegment current carrying region having substantially the same currentcarrying capacity as said one stripe, thereby to reduce the effects of alloying on the surface state density in the underlying substrate to increase inversion voltage at said selected region.
Claim 2
Dependent Claim
122 words
In a semiconductor integrated circuit array comprising a semiconductor substrate, an insulating layer disposed over said substrate, a plurality of semiconductor devices integrated on said substrate and operatively electrically connected by a plurality of conductive stripes disposed on said insulating layer, said conductive stripes comprising an active metal alloyed at an elevated temperature on said insulating layer, the improvement comprising a selected region of at least one of said stripes being divided into a plurality of narrower stripes electrically connected in parallel defining a multisegment current carrying region having substantially the same currentcarrying capacity as said one stripe, thereby to reduce the effects of alloying on the surface state density in the underlying substrate to increase inversion voltage at said selected region.
Claim 3
Dependent Claim
12 words
The integrated circuit array of claim 1, wherein said substrate is silicon.
Claim 4
Dependent Claim
14 words
The integrated circuit array of claim 2, wherein said insulating layer is silicon dioxide.
Claim 5
Dependent Claim
13 words
The integrated circuit array of claim 3, wherein said active metal is aluminum.
Claim 6
Dependent Claim
66 words
The integrated circuit array of claim 1, wherein said semiconductor substrate is of one conductivity type semiconductor material and at least two functionally unrelated spaced regions of the opposite conductivity type semiconductor material diffused in said substrate spaced from one another and functionally unrelated, said multisegment current carrying region of said at least one conductive stripe being defined in the area between said two diffused regions.
Claim 7
Dependent Claim
20 words
The integrated circuit array of claim 5, wherein said substrate is n-type material and said diffused regions are p-type material.
Claim 8
Dependent Claim
21 words
The integrated circuit array of claim 1, wherein at least some of said semiconductor devices are insulated gate field effect transistors.
Claim 9
Dependent Claim
21 words
The integrated circuit array of claim 7, wherein said insulated gate field effect transistors are of the metal oxide silicon type.
Claim 10
Dependent Claim
17 words
The integrated circuit array of claim 1, wherein said insulating layer is from 14,000-16,000 A. in thickness.
Claim 11
Dependent Claim
12 words
The integrated circuit array of claim 9, wherein said substrate is silicon.
Claim 12
Dependent Claim
14 words
The integrated circuit array of claim 10, wherein said insulating layer is silicon dioxide.
Claim 13
Dependent Claim
13 words
The integrated circuit array of claim 11, wherein said active metal is aluminum.
Claim 14
Dependent Claim
66 words
The integrated circuit array of claim 12, wherein said semiconductor substrate is of one conductivity type semiconductor material and at least two functionally unrelated spaced regions of the opposite conductivity type semiconductor material diffused in said substrate spaced from one another and functionally unrelated, said multisegment current carrying region of said at least one conductive stripe being defined in the area between said two diffused regions.
Claim 15
Dependent Claim
97 words
A semiconductor integrated circuit array including a semicondcutor substrate, a layer of insulating material disposed on said substrate, a plurality of semiconductor devices integrated on said substrate, and electrically conductive means operatively electrically connected to at least one of said semiconductor devices, said conductive means being disposed on said insulating layer and having at least one region comprising plurality of segments electrically connected in parallel, and having substantually the same current carrying capability as said conductive means, each of said segments being not more than 0.2 mils wide in a direction transverse to their current carrying direction.
Claim 16
Dependent Claim
97 words
A semiconductor integrated circuit array including a semicondcutor substrate, a layer of insulating material disposed on said substrate, a plurality of semiconductor devices integrated on said substrate, and electrically conductive means operatively electrically connected to at least one of said semiconductor devices, said conductive means being disposed on said insulating layer and having at least one region comprising plurality of segments electrically connected in parallel, and having substantually the same current carrying capability as said conductive means, each of said segments being not more than 0.2 mils wide in a direction transverse to their current carrying direction.
Claim 17
Dependent Claim
63 words
The integrated circuit array of claim 14, wherein said semiconductor substrate comprises one conductivity type material and further comprising at least two regionS of the opposite conductivity type material diffused in said substrate spaced from one another and functionally unrelated, and wherein said at least one region of said conductive means is disposed in the area between said diffused regions in said substrate.
References Cited (Backward Citations)
US3450965A
Cited
US3430115A
Cited
US3533088A
Cited
US3519890A
Cited
US3546543A
Cited
US3564354A
Cited
US3675091A
Cited
US3644804A
Cited
US3657614A
Cited
US3693048A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-15 | 1977-04-16 | 1977-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-15 | 1981-04-16 | 1981-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-15 | 1985-04-16 | 1985-10-16 | $7700.00 | Window Closed / Lapsed |