Abstract A method for fabricating dielectric isolated integrated devices which allows the formation of a truly planar surface. The method includes etching isolation channels in a semiconductor substrate through a suitable mask. The mask pattern is designed to enhance deeper etching at certain locations in the isolation channels. A dielectric layer is formed over the exposed surfaces of the isolation channels and a semiconductor material is grown in the channels. The deeper etched locations which are now filled with dielectric isolation are used as a depth guide in the formation of a dielectric layer from the semiconductor substrate surface opposite to the one from which the etching took place. The depth guide can be used in either a deep etch or lap-back process. The last isolation step is then to continue the dielectric layer past the depth guide to the major portion of the isolation channels to produce the fully isolated islands of semiconductor material in the semiconductor substrate.
A planar dielectrically isolated semiconductor intermediate structure comprising: a plurality of isolated islands of semiconductor material; said islands being separated from one another by isolation channel regions of dielectric material; the surface layer of said regions contiguous to said islands being composed of a dielectric material deposited at a different time than the bulk of said regions of dielectric material; a planar surface dielectric layer covering the entire surface of said structure to fully isolate said islands; and said contiguous layer extending into said surface dielectric layer at corners in said isolation channel regions.
Claim 2
Dependent Claim
94 words
A planar dielectrically isolated semiconductor intermediate structure comprising: a plurality of isolated islands of semiconductor material; said islands being separated from one another by isolation channel regions of dielectric material; the surface layer of said regions contiguous to said islands being composed of a dielectric material deposited at a different time than the bulk of said regions of dielectric material; a planar surface dielectric layer covering the entire surface of said structure to fully isolate said islands; and said contiguous layer extending into said surface dielectric layer at corners in said isolation channel regions.
Claim 3
Dependent Claim
40 words
The planar dielectrically isolated semiconductor intermediate structure of claim 1 wherein said islands are silicon, said contiguous layer of said regions is silicon dioxide, the remaining portions of said regions are polycrystalline silicon and said surface layer is silicon dioxide.