Digital dial pulse distortion corrector

Claim 2

A digital dial pulse distortion corrector to generate output dial pulses having a constant break-to-make ratio in response to input dial pulses having a given range of break-to-make ratios and a given range of repetition rates comprising: a first source of said input dial pulses; a second source of clock pulses having a given repetition rate; and logic circuitry coupled to said first and second sources to control the generation of said output dial pulses; said logic circuitry including a first binary counter coupled to said second source, a first logic circuit coupled to said first binary counter and said first source responsive to the leading edge of said input dial pulses to control the operation of said first binary counter and to produce a first control signal having a given width, a second binary counter coupled to said second source, said second binary counter having a controllable counting rate, and a second logic circuit coupled to said first source, to said first logic circuit and to said second binary counter, said second logic circuit being responsive to said leading edge of said input dial pulses and said first control signal to generate said output dial pulses and to control the counting rate of said second binary counter said second binary counter controlling the generation of said output dial pulses.

Claim 3

A dial pulse corrector according to claim 1 wherein said second binary counter has two different counting rates, and said second logic circuit includes a pair of interconnected bistable means coupled to said first source, to said second binary counter and to said first logic circuit, said pair of Bistable means being responsive to said first control signal being time coincident with one of said input dial pulses to set said second binary counter to the slower of said two counting rates and being responsive to said first control signal being time coincident with another of said input dial pulses immediately adjacent said one of said input dial pulses to set said second binary counter to the faster of said two counting rates.

Claim 4

A dial pulse corrector according to claim 1, wherein said first binary counter includes a first binary divider having a first given division factor to produce a binary ''''1'''' condition after a first given time delay, and a second binary divider having a second given division factor coupled to said first binary divider to produce a binary ''''1'''' condition after a second given time delay; and said first logic circuit includes a first bistable device coupled to said first source responsive to the leading edge of said input dial pulses to produce a binary ''''1'''' condition, a second bistable device coupled to said first source, said first bistable device and said first and second binary dividers to reset said first bistable device and said first and second binary dividers upon occurrence of the leading edge of said input dial pulses, a first logic gate coupled to said second source, said first bistable device and said first binary divider to control the coupling of said clock pulses to said first binary divider, and a second logic gate coupled to said first binary divider and said second binary divider to produce said first control signal having said given width equal to the sum of said first and second time delays, said first control signal being coupled to said first bistable device to maintain said binary ''''1'''' condition thereof until the end of said given width.

Claim 5

A dial pulse corrector according to claim 3, wherein said first and second binary dividers includes D-type flip flops; said first and second bistable devices each include a D-type flip flop; and said first and second logic gates each include a NAND gate.

Claim 6

A dial pulse corrector according to claim 3, wherein said second binary counter includes a third binary divider having a third given division factor to provide a slow counting rate, a fourth binary divider having a fourth given division factor to provide a fast counting rate, and a fifth binary divider having a fifth given division factor to produce a binary ''''1'''' condition after a first given count; and said second logic circuit includes a third logic gate coupled to said second source, said fifth binary divider and said third and fourth binary divider, a third bistable device coupled to said second logic gate responsive to said first control signal to produce a first counting rate control signal upon occurrence of the time coincidence of said first control signal and one of said input dial pulses and a second counting rate control signal upon occurrence of the time coincidences of said first control signal and another of said input dial pulses immediately adjacent to said one of said input dial pulses, a fourth bistable device coupled to said first source, a fifth bistable device coupled to said second logic gate, said third and fourth bistable devices and said third, fourth and fifth binary dividers responsive to the complement of said first control signal to reset said third and fourth bistable devices and said third, fourth and fifth binary dividers, a fourth logic gate having its output coupled to the input of said fifth binary divider, a fifth logic gate having its output coupled to one input of said fourth logic gate, one input coupled to said third binary divider and its second input coupled to said third bistable device responsive to said first counting rate control signal, a sixth logic gate having its output coupled To a second input of said fourth logic gate, one input coupled to said fourth binary divider and its second input coupled to said third bistable device responsive to said second counting rate control signal, and a seventh logic gate coupled to said fifth binary divider, said fourth bistable device and said third bistable device responsive to said second counting rate control signal to control said fourth bistable device to produce said output dial pulses.

Claim 7

A dial pulse corrector according to claim 5, wherein said third, fourth and fifth dividers includes D-type flip flops; said third, fourth and fifth bistable devices each include a D-type flip flop; and said third, fourth, fifth, sixth and seventh logic gates each include a NAND gate.

Claim 8

A dial pulse corrector according to claim 5, wherein said first source further provides in the absence of said input dial pulses a binary ''''1'''' condition for a period of time greater than a given period of time; said second binary counter further includes a sixth binary divider having a sixth given division factor to produce a binary ''''1'''' condition after said given period of time; and further including a third logic circuit including a sixth bistable device coupled to said first source responsive to the trailing edge of said input dial pulses, an eighth logic gate coupled to said sixth bistable device, said first source and one of said first and second binary divider responsive to the trailing edge of said input dial pulses and the binary ''''1'''' condition after one of said first and second time delays, a ninth logic gate coupled to said sixth bistable device and said clock pulses, a seventh binary divider having a seventh given division factor to produce a binary ''''1'''' condition after a selected time delay, and a tenth logic gate having its inputs coupled to said sixth binary divider, said seventh binary divider and said first source and its output coupled to said fourth bistable device to reset said fourth bistable device after said given period of time.

Claim 9

A dial pulse corrector according to claim 7, wherein said sixth and seventh binary dividers include D-type flip flops; said sixth bistable device includes a D-type flip flop; and said eighth, ninth and tenth logic gates each include a NAND gate.