US3764986A
Expired / Lapsed
US
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Magnetic tape data processing system
Assignee: MI2 COLUMBUS
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Filing: 1972-08-09
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Granted: 1973-10-09
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Expires: 1992-08-09
Abstract
Abstract There is disclosed a data handling system for use as a terminal or word processor including input-output means, intermediate memory and a magnetic tape cassette principal memory. Incoming data is accumulated alternately in one of the intermediate memories until its capacity is reached, then the data block is transferred to the principal memory at a high speed. An inverse sequence is followed for playback. For data editing, a special editing memory and associated control logic are provided. Blocks of data are transferred from the principal memory to one of the intermediate memories. The data is entered in the editing memory either continuously or on a character-by-character basis controlled by the user. Data may be added or deleted as desired, after which, individual data blocks are returned to the principal memory. (Space in the latter is automatically allowed when data is recorded to accommodate added characters.) During editing, line length adjustment is provided by converting ''''spaces'''' near the end of an edited line into ''''carrier returns''''. Carrier returns far from the end of an edited line become ''''spaces''''. Search capability based on selectable identifying characters, both in forward and reverse directions of tape travel is also available. Searches may be part of the editing operation or simply in preparation for editing or a normal playback.
Inventors
- 👤 C Spademan
- 👤 J Marsalka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:39
CPC Classifications
B; B41; B41B; B41B27/00; B41J; B41J3/00; B41J3/44; B41J3/50; B41J5/00; B41J5/30; B41J5/31; B41J5/40; B41J5/42
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
232 words
Processing means for digital data in the form of multibit character code words comprising: a principal memory having a magnetic tape as the memory medium; input-output means; an intermediate memory having capacity for storing a data block comprising a plurality of code words; an editing memory having capacity for storing a plurality of data blocks substantially less in number than the principal memory; and editing operation control means including means to effect transfer from said principal memory to said intermediate memory of a single block of data, means for transferring data from said intermediate memory to said editing memory, first logic means responsive to external commands to control the quantity of data transferred from said intermediate memory, second logic means responsive to external commands transferring data from said intermediate memory while inhibiting said editing memory to prevent storage of data transferred thereto from said intermediate memory, third logic means for actuating said editing memory to receive data from an external source through said input-output means, fourth means responsive to transfer of said data block from said intermediate memory and to accumulation of complete data block in said editing memory to transfer a complete data block from said editing memory back to said principal memory through said intermediate memory, and means responsive to transfer of said data block to said principal memory to transfer the next unedited data block to said intermediate memory.
Claim 2
Dependent Claim
232 words
Processing means for digital data in the form of multibit character code words comprising: a principal memory having a magnetic tape as the memory medium; input-output means; an intermediate memory having capacity for storing a data block comprising a plurality of code words; an editing memory having capacity for storing a plurality of data blocks substantially less in number than the principal memory; and editing operation control means including means to effect transfer from said principal memory to said intermediate memory of a single block of data, means for transferring data from said intermediate memory to said editing memory, first logic means responsive to external commands to control the quantity of data transferred from said intermediate memory, second logic means responsive to external commands transferring data from said intermediate memory while inhibiting said editing memory to prevent storage of data transferred thereto from said intermediate memory, third logic means for actuating said editing memory to receive data from an external source through said input-output means, fourth means responsive to transfer of said data block from said intermediate memory and to accumulation of complete data block in said editing memory to transfer a complete data block from said editing memory back to said principal memory through said intermediate memory, and means responsive to transfer of said data block to said principal memory to transfer the next unedited data block to said intermediate memory.
Claim 3
Dependent Claim
55 words
A data processor as defined in claim 1 wherein said first logic means includes first means responsive to an external command for transferring data from said intermediate memory continuously until halted bY a further external command, and second means responsive to another external command to transfer a single character code word from said intermediate memory.
Claim 4
Dependent Claim
84 words
A data processor as defined in claim 1 wherein said second logic means includes means responsive to a first external command to transfer a single character code word from said intermediate memory, and means responsive to other external commands for transferring data continuously from said intermediate memory, means to identify certain characters being transferred from said intermediate memory, and means responsive to particular external commands to halt transfer of data from said intermediate memory upon identification of an associated one of said certain characters.
Claim 5
Dependent Claim
116 words
A data processor as defined in claim 3 further including buffer means coupling said intermediate memory and said editing memory, and adapted to receive data one bit at a time, and wherein said identifying means comprises a read only memory for storing the code words for said certain characters, data comparison means coupled to said read only memory and to said buffer means, and operative to provide an indication whenever data coincidence is detected, means for scanning the addresses of said read only memory at a rate substantially exceeding the input bit rate to said buffer, and means responsive to a coincidence indication to identify the particular read only memory address for which said coincidence occurred.
Claim 6
Dependent Claim
76 words
A data processor as defined in claim 1 further including fifth logic means responsive to an external command and to incoming data from said input-output means to store a search reference code, means responsive to completion of storage of said reference code to initiate continuous transfer of data from said intermediate memory, and identification means for comparing the data being transferred from said intermediate memory and for halting said transfer upon recognition of said reference code.
Claim 7
Dependent Claim
55 words
A data processor as defined in claim 1 wherein said fourth logic means includes means responsive to transfer of a complete data block from said intermediate memory and accumulation of less than a complete data block in said editing memory for transferring the next unedited data block from said principal memory to said intermediate memory.
Claim 8
Dependent Claim
61 words
A data processor as defined in claim 1 wherein a plurality of data blocks comprising a complete message carries a particular terminal code word and wherein said fourth logic means includes means responsive to the entry of saiD terminal code word into said editing memory to transfer all data in said editing memory to said principal memory through said intermediate memory.
Claim 9
Dependent Claim
170 words
A data processor as defined in claim 1 including adjusting means for establishing a printout line length format, means for counting the number of characters stored in the editing memory since the end of a previous line and to provide an indication when a predetermined number has been counted, means for identifying first and second character code words being transferred out of said intermediate memory, means for generating the code words for said first and second characters, means responsive to identification of said first character in the absence of said predetermined count indication to suppress entry of said first character in said editing memory and to actuate said generating means to enter the code word for the second character into the editing memory, and means responsive to identification of said second character in the presence of said predetermined count indication to suppress entry of said second characters in said editing memory and to actuate said generating means to enter the code words for the first character into the editIng memory.
Claim 10
Dependent Claim
39 words
A data processor as defined in claim 8 further including means responsive to identification of either said first or said second characters to suppress operation of said adjusting means for the immediately following character transferred from said intermediate memory.
Claim 11
Dependent Claim
139 words
A data processor as defined in claim 8 wherein said means for identifying said first and second character code words includes buffer means coupling said intermediate memory to said editing memory, and operable to receive data one bit at a time, a read only memory containing the code words for said first and second characters, data comparison means coupled to said read only memory and said buffer and operative to provide an indication whenever data coincidence is detected, means for scanning the addresses of said read only memory to render accessible to said data comparison means all the data stored in said read only memory, said scanning occurring at a rate substantially exceeding the input bit rate for said buffer, and means responsive to said coincidence indication to identify the particular read only memory address for which coincidence occurred.
Claim 12
Dependent Claim
62 words
A data processor as defined in claim 10 wherein said generating means comprises said read only memory and the addressing means therefor, the latter being actuated when one of said first or second characters is to be generated, and also including logic means responsive to generation of said first or second character as required to halt the operation of said addressing means.
Claim 13
Dependent Claim
44 words
A data processor as defined in claim 1 further including a read only memory for storing code words for a plurality of characters and addressing means for said read only memory comprising counting means having a rest state and a plurality of active states.
Claim 14
Dependent Claim
101 words
A data processor as defined in claim 12 including buffer means, means for coupling said buffer means to the input or the output of said intermediate memory, switching means for coupling the output of said read only memory to the input of said buffer means, and means for entering a code word from said read only memory into said buffer means comprising logic means responsive to a command to actuate said addressing means, and means responsive to a particular address being reached for actuating said switching means and said buffer means to receive in the latter, the read only memory output.
Claim 15
Dependent Claim
183 words
A data processor as defined in claim 1 wherein said editing operation control means includes means for establishing a sequence of editing modes, a first mode being established responsive to an external command, said control means being responsive to establishment of said first mode to transfer said block of data to said intermediate memory from said principal memory, means responsive to transfer a complete block of data to said intermEdiate memory for establishing a second editing mode, said control means being responsive to establishment of said second mode and to the various external commands to transfer data out of said intermediate memory, said fourth logic means being operative to establish a third editing mode during which data is returned to said intermediate memory, followed by a fourth mode during which data is transferred from said intermediate memory to said principal memory, and responsive to completion of said fourth mode or to transfer of a complete data block from said intermediate memory, and accumulation of less than a complete data block in said editing memory to return said system to said first editing mode.
Claim 16
Dependent Claim
109 words
A data processor as defined in claim 14 Wherein a plurality of data blocks comprising a complete message carries a particular terminal code word, and wherein said fourth logic means includes means for sensing said terminal code word, as it enters said editing memory when said system is operating in said second editing mode and responsive thereto to transfer said system to said third mode, and thereafter to cycle said system between modes three and four, means for sensing when all data in said editing memory has been transferred to said intermediate memory, and for terminating editing operation at the end of the mode four state following such transfer.
Claim 17
Dependent Claim
91 words
A data processor as defined in claim 14 wherein said principal memory includes a tape transport, a playback head and a record head disposed upstream of said playback head, wherein data is stored in said principal memory with gaps separating successive data blocks, and including means responsive to entry of the system into editing operation to reverse said tape transport until the tape is positioned with the playback head at the beginning of the first data block to be edited, and for thereafter establishing the system in said first editing mode.
Claim 18
Dependent Claim
37 words
A data processor as defined in claim 16 including means responsive to termination of editing operation and immediate reestablishment thereof with no intervening operation to inhibit the tape reversal prior to establishment of said first editing mode.
Claim 19
Dependent Claim
68 words
A data processor as defined in claim 14 wherein said principal memory includes a tape transport, and playback and record heads, and including means responsive to entry of the system into said second editing mode to reverse said tape transport until said tape is positioned with said record head at the beginning of the data block transferred to the intermediate memory during the immediately previous edit mode one.
Claim 20
Dependent Claim
77 words
A data processor as defined in claim 14 wherein said input/output means includes buffer means coupling said intermediate memory to said editing memory, and means for actuating said buffer means to receive and emit data on a bit by bit basis, and wherein said intermediate memory and said editing memory are each random access memories and each include addressing means comprising counters for rendering accessible the memory sites in a predetermined order for data storage and retrieval.
Claim 21
Dependent Claim
91 words
A data processor as defined in claim 19 including data transfer clock means including first means for generating control pulses in groups equal in number to the number of bits in a code word, and second means for generating a continuous succession of control pulses, and means for operating said intermediate memory, said buffer, and said editing memory in response to said groups of control pulses during edit mode two, and for operating said intermediate and editing memories in response to said succession of control pulses during the other edit modes.
Claim 22
Dependent Claim
41 words
A data processor as defined in claim 20 including means for inhibiting operation of said editing memory for the first group of control pulses generated during each edit mode two to allow data from the intermediate memory to fill the buffer.
Claim 23
Dependent Claim
142 words
A data processor as defined in claim 20 including means for providing data from an external source during edit mode twO to the input of said buffer, means responsive to the provision of a first character code word from said external source for inhibiting data transfer to said editing memory until said first code word has been entered in said buffer, means responsive to entry of an external character code word to actuate said buffer and said editing memory in response to a group of control pulses, and logic means responsive to a first group of control pulses for external data entry following an editing operation other than external entry for reducing the count of the addressing means for said intermediate memory for each pulse of said group, and for thereafter inhibiting operation of said intermediate memory until external data entry ceases.
Claim 24
Dependent Claim
81 words
A data processor as defined in claim 20 including means for generating a signal in response to the addressing means for the intermediate memory corresponding to the last bit of a data block, means responsive to said signal during edit mode two for operating said buffer and said editing memory in response to an additional group of control pulses, and means responsive to the end of said additional group of control pulses for transferring the system to the third edit mode.
Claim 25
Dependent Claim
86 words
A data processor as defined in claim 20 wherein said first logic means is operative only during edit mode two, and includes means responsive to a first external command to operate said intermediate memory, said buffer, and editing memory in response to successive groups of control pulses, and responsive to a second external command to terminate said operation and means responsive to termination of an edit mode two during such continuous operation for reinitiating said continuous during the next edit mode two in the editing cycle.
Claim 26
Dependent Claim
155 words
A data processor as defined in claim 24 wherein said first logic means further includes means responsive to a plurality of additional external commands to operate said intermediate memory and said buffer in response to said groups of control pulses but to inhibit operation of said editing memory, said means being responsive to a first of said additional commands to operate said intermediate memory and said buffer but to inhibit said editing memory for one group of said control pulses, and additional means coupled to said buffer for indicating the presence of certain character code words therein, said first logic means being responsive to others of said external commands to operate said intermediate memory and said buffer and to inhibit said editing memory in response to successions of groups of control pulses until the presence of respective ones of said character code words has been detected, and for one additional group of control pulses thereafter.
Claim 27
Dependent Claim
39 words
A data processor as defined in claim 25 further including means responsive to termination of an edit mode two during one of the aforesaid operations for reinitiating said operation during the next edit mode two in the edit cycle.
Claim 28
Dependent Claim
108 words
A data processor as defined in claim 26 wherein said additional means comprises a read only memory containing said certain character code words in respective memory sites, comparison means coupled to the outputs of said buffer and said read only memory, means for addressing said memory sites in succession, means for operating said addressing means at a rapid rate in relation to the repetition rate of said control pulses, means to generate an indication of a match between the data in said buffer and in said read only memory, and means responsive to said match indication to identify the read only memory address for which said match occurred.
Claim 29
Dependent Claim
38 words
A data processor as defined in claim 24 wherein said first logic means further includes means responsive to another external command to operate said intermediate memory, said buffer and said editing memory for one group of control pulses.
Claim 30
Dependent Claim
152 words
A data processor as defined in claim 19 further including means for entering data from an external source into said buffer, special memory means having its input connected to sAid buffer, means responsive to a special external command for entering said external data into said special memory, means responsive to entry of a desired number of character code words in said special memory during edit mode two for initiating continuous transfer of data from said intermediate memory through said buffer to said editing memory, and for continuing said transfer through successive entries of the system into edit mode two, comparison means coupled to said special memory and said buffer and responsive to a match between the data therein to generate a control signal, and means responsive to said control signal to advance said editing memory, said buffer, and said intermediate memory to transfer one additional character code word to said editing memory.
Claim 31
Dependent Claim
30 words
A data processor as defined in claim 29 including means for inhibiting operation of said editing memory for the first character code word following initiation of said continuous data transfer.
Claim 32
Dependent Claim
68 words
A data processor as defined in claim 20 wherein said editing memory is comprised of a plurality of bit storage sites and addressing means for rendering said sites accessible in sequence for data storage, contents counting means comprising an up down counter, means for advancing said up down counter during edit mode two, and means for reducing the count of said up down counter during edit mode three.
Claim 33
Dependent Claim
129 words
A data processor as defined in claim 31 further including first and second count memories connected to said addressing means for said editing memory, means reponsive to the end of an edit mode two for storing the address of said editing memory site last accessed in said first count memory, means responsive to the end of an edit mode three for storing the address of said editing memory site last accessed in said second count memory, means responsive to the beginning of an edit mode two to set the editing memory addressing means to the address stored in said first count memory, and means responsive to the beginning of an edit mode three to set the editing memory addressing means to the address stored in said second count memory.
Claim 34
Dependent Claim
271 words
Processing means for digital data in the form of multibit code word comprising: a principal memory having a magnetic tape transport for carrying a magnetic tape as a memory medium, playback and recording heads; an intermediate memory for storing a block of data comprised of a plurality of code words; input/output means including a buffer for storing a predetermined small number of code words, means for selectively coupling the input of said buffer to the output of said intermediate memory or to an external data source; special memory means having a capacity equal to those of the buffer; comparison means connected to the outputs of said buffer and said special memory; and search control logic means including means responsive to an external command to connect said buffer to said external source, means responsive to entry of data to said buffer from said external source to store said data in said special memory, means responsive to storage of said data in said special memory to initiate operation of said tape transport and said playback head to load a data block from said tape to said intermediate memory, means responsive to loading of said intermediate memory to couple said buffer to said intermediate memory and to transfer data to said buffer, means responsive to a match between the data in said buffer and that in said special memory to terminate data transfer to said intermediate memory, and means responsive to transfer of an entire data block from said intermediate memory without a data match to operate said tape transport and said playback head to transfer another block of data to said intermediate memory.
Claim 35
Dependent Claim
271 words
Processing means for digital data in the form of multibit code word comprising: a principal memory having a magnetic tape transport for carrying a magnetic tape as a memory medium, playback and recording heads; an intermediate memory for storing a block of data comprised of a plurality of code words; input/output means including a buffer for storing a predetermined small number of code words, means for selectively coupling the input of said buffer to the output of said intermediate memory or to an external data source; special memory means having a capacity equal to those of the buffer; comparison means connected to the outputs of said buffer and said special memory; and search control logic means including means responsive to an external command to connect said buffer to said external source, means responsive to entry of data to said buffer from said external source to store said data in said special memory, means responsive to storage of said data in said special memory to initiate operation of said tape transport and said playback head to load a data block from said tape to said intermediate memory, means responsive to loading of said intermediate memory to couple said buffer to said intermediate memory and to transfer data to said buffer, means responsive to a match between the data in said buffer and that in said special memory to terminate data transfer to said intermediate memory, and means responsive to transfer of an entire data block from said intermediate memory without a data match to operate said tape transport and said playback head to transfer another block of data to said intermediate memory.
Claim 36
Dependent Claim
143 words
A data processor as defined in claim 33 wherein said intermediate memory comprises a random access memory unit and addressing means comprising an up-down counter, said memory being responsive to a particular count to render accessible a corresponding memory site, for data sTorage or retrieval, means for setting said counter at a predetermined initial count, and means for advancing said counter from said initial count, and for actuating said random access memory to store the data output of said tape on a bit by bit basis in successive memory sites, and wherein said means for transferring data to said buffer from said intermediate memory comprises means to set said counter to said initial count, and means for advancing said counter, and for operating said random access memory and said buffer to enter the contents of each memory site in turn into said buffer.
Claim 37
Dependent Claim
64 words
A data processor as defined in claim 34 wherein said tape transport is run so the tape moves in the same direction as when the data thereon was originally recorded, and further including means responsive to said external command and to another external command to operate said tape transport so the tape runs in the direction opposite to that when the data was recorded.
Claim 38
Dependent Claim
58 words
A data processor as defined in claim 35 further including means responsive to said other external command to cause said up-down counter to be set to a count equal to the number of bits in a data block and to operate said counter to reduce the count therein when said random access memory receives data from said tape.
Claim 39
Dependent Claim
76 words
A data processor as defined in claim 36 including means responsive to a data match during an operation initiated by both of said external commands to initiate operation of said tape transport in said normal direction, and storage in said random access memory beginning at the memory site corresponding to the initial count of said counter, and for continuing such operation until a match again occurs between the data in said buffer and said special memory.
Claim 40
Dependent Claim
58 words
A data processor as defined in claim 37 wherein said intermediate memory comprises two separate random access memories and associated addressing means, and further including cycling means operative to permit transfer of data from one of said random access memories to said buffer while data from said tape is transferred to the other of said random access memories.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |