Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
247 words
In Combination: first and second latch circuits each having an input point, an output point, and a control point; said first and second latch circuits each being responsive to a first signal condition at said respective control points for providing a conductive path from said respective input points to said respective output points and to a second signal condition at said respective control points for providing a non-conductive condition between said respective input points and said respective output points, said first and second latcH circuits being further responsive to said signal condition at said respective control points changing from said first signal condition to said second signal condition for maintaining the signal condition at said respective output points not withstanding further changes in the signal condition at said respective input points until said signal condition at said respective control points revert to said first signal condition; means for connecting said output point of said first latch circuit to said input point of said second latch circuit; and means for successively applying (1) said first signal condition to said control points of said first and second latch circuit during a first time interval, (2) said first signal condition to said control point of said first latch circuit and said second signal condition to said control point of said second latch circuit during a second time interval and (3) said second signal condition to said control points of said first and second latch circuits during a third time interval.
Claim 2
Dependent Claim
247 words
In Combination: first and second latch circuits each having an input point, an output point, and a control point; said first and second latch circuits each being responsive to a first signal condition at said respective control points for providing a conductive path from said respective input points to said respective output points and to a second signal condition at said respective control points for providing a non-conductive condition between said respective input points and said respective output points, said first and second latcH circuits being further responsive to said signal condition at said respective control points changing from said first signal condition to said second signal condition for maintaining the signal condition at said respective output points not withstanding further changes in the signal condition at said respective input points until said signal condition at said respective control points revert to said first signal condition; means for connecting said output point of said first latch circuit to said input point of said second latch circuit; and means for successively applying (1) said first signal condition to said control points of said first and second latch circuit during a first time interval, (2) said first signal condition to said control point of said first latch circuit and said second signal condition to said control point of said second latch circuit during a second time interval and (3) said second signal condition to said control points of said first and second latch circuits during a third time interval.
Claim 3
Dependent Claim
48 words
The combination as defined in claim 1 also including: means for applying a first information signal to said input point of said first latch circuit during said first interval and a second information signal to said input point of said first latch circuit during said second time interval.
Claim 4
Dependent Claim
46 words
The combination as defined in claim 1 in which said successive applying means applies said second signal condition to said control point of said first latch circuit and said first signal condition to said control point of said second latch circuit during a fourth time interval.
Claim 5
Dependent Claim
48 words
The combination as defined in claim 3 also including: means for applying a first information signal to said input point of said first latch circuit during said first interval and a second information signal to said input point of said first latch circuit during said second time interval.
Claim 6
Dependent Claim
77 words
The combination as defined in claim 4 in which said successive applying means includes: a shift register having first and second shift register stages or shifting level signals applied thereto from said first stage to said second stage; means for connecting said first stage of said shift register to said control point of said second latch circuit; and means for connecting said second stage of said shift register to said control point of said first latch circuit.
Claim 7
Dependent Claim
38 words
The combination as defined in claim 5 also including: means for normally applying a first level signal to said shift register, responsive to said information signal applying means for applying a second level signal to said shift register.
Claim 8
Dependent Claim
68 words
The combination as defined in claim 6 also including: a plurality of latch circuits connected in cascade with each other and with said first and second latch circuits, each of said plurality of latch circuits having a control point; and said shift register has one stage for each latch circuit, each of said shift register stages being connected to a control point of one of said latch circuits.
Claim 9
Dependent Claim
90 words
The combination as defined in claim 6 in which said first and second latch circuits have a plurality of input points and a plurality of output points, each of said respective input points being associated with one of said respective output points, said control point controlling the electrical relationship between each pair of input points and output points in a like manner, said combination also including: means for connecting each of said output points of said first latch circuit to one of said input points of said second latch circuit.
Claim 10
Dependent Claim
68 words
The combination as defined in claim 8 also including: a plurality of latch circuits connected in cascade with each other and with said first and second latch circuits, each of said plurality of latch circuits having a control point; and said shift register has one stage for each latch circuit, each of said shift register stages being connected to a control point of one of said latch circuits.