US3764792A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for adding two delta coded signals
Assignee: International Business Machines Corp
•
Filing: 1971-12-15
•
Granted: 1973-10-09
•
Expires: 1991-12-15
Abstract
Abstract A method of adding two delta coded signals having the same binary bit rate. Whenever corresponding bits of two delta coded signals are to be added and both have the same binary value, a bit of this value is generated. Each time the bits of said two delta coded signals are different, a zero bit or a one bit is generated alternately. An adding circuit including two channels is disclosed to perform the method. One of the channels is constructed to provide a binary output signal when the bits of the delta coded signals are the same, and the other channel is constructed to provide a binary output signal when bits of the delta coded signals are different. The output of the two channels are combined to obtain the half-sum of the delta coded signals which can be used in digital recursive filtering techniques.
Inventors
- 👤 C Jacquart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:29
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/06; H04B14/062; H04B14/064; G; G06; G06F; G06F7/00; G06F7/60; G06F7/64
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
168 words
An adding circuit to add two data coded signals having the same binary bit rate to provide an output sum signal at the same binary bit rate as the two signals comprising: mismatch channel means receiving the two signals to be added and generating a bit of one value during a bit time where bits of the two signals to be added are different and alternately generating a bit of another value during a next bit time where bits of the two signals to be added are different; match channel means receiving the two signals to be added and generating, a one bit each time bits at corresponding bit times of the two signals to be added are one bits, and a zero bit each time bits at corresponding bit times of the two signals to be added are zero bits; and an output device connected to an output of the mismatch channel means and an output of the match channel means for generating the output sum signal.
Claim 2
Dependent Claim
168 words
An adding circuit to add two data coded signals having the same binary bit rate to provide an output sum signal at the same binary bit rate as the two signals comprising: mismatch channel means receiving the two signals to be added and generating a bit of one value during a bit time where bits of the two signals to be added are different and alternately generating a bit of another value during a next bit time where bits of the two signals to be added are different; match channel means receiving the two signals to be added and generating, a one bit each time bits at corresponding bit times of the two signals to be added are one bits, and a zero bit each time bits at corresponding bit times of the two signals to be added are zero bits; and an output device connected to an output of the mismatch channel means and an output of the match channel means for generating the output sum signal.
Claim 3
Dependent Claim
109 words
An adding circuit as claimed in claim 1 to add two delta coded signals having the same binary bit rate to provide an output delta coded sum signal wherein the mismatch channel means comprises: actuating means receiving the two delta coded signals to be added and generating a bit each time the bits of said delta coded signals are different; a memory circuit generating and recording a value of a last bit generated by the mismatch channel means, and addressing means connected to the actuating means and to the memory means for modifying the information recorded in the memory device, whenever a bit is received from the actuating means.
Claim 4
Dependent Claim
36 words
An adding circuit as claimed in claim 2 in which the actuating means is an EXCLUSIVE OR gate generating a bit each time corresponding bits of the two delta coded signals to be added are different.
Claim 5
Dependent Claim
49 words
An adding circuit as claimed in claim 2 in which the memory circuit is a flip flop generating alternately one bits and zero bits which are the output signals of the mismatch channel means and staying in the state corresponding to the type of bit which has been generated.
Claim 6
Dependent Claim
68 words
An adding circuit as claimed in claim 2 in which the addressing means comprises two AND gates connected to the memory circuit to form with said memory circuit, a binary decision logic circuit, the two AND gates being responsive to a signal generated by the actuating means and to timing pulses having a rate which is equal to a rate of the delta coded signals to be added.
Claim 7
Dependent Claim
146 words
An adding circuit as claimed in claim 2 which comprises: an EXCLUSIVE OR gate receiving the two delta coded signals to be added and generating a bit each time corresponding bits of the delta coded signals are different; a flip flop generating alternately a one bit and a zero bit which are output signals of the mismatch channel means, and staying in a state corresponding to a type of bit which has been generated during a preceding mismatch of the two delta coded signals to be added; and two AND gates connected to the flip flop to form a binary decision logic circuit, the AND gates also being connected to the EXCLUSIVE OR gate and responsive to bits generated by the EXCLUSIVE OR gate and to timing pulses having a rate which is equal to a rate of the two delta coded signals to be added.
Claim 8
Dependent Claim
69 words
An adding circuit as claimed in claim 6 wherein: the match channel means is an AND gate for receiving two delta coded signals to be added and generating the output signal of said match channel means, and; the output device is an OR gate connected to the output of the mismatch channel means and the output of the match channel means for generating the output delta coded sum signal.
Claim 9
Dependent Claim
37 words
An adding circuit as claimed in claim 2 in which the match channel means is an AND gate receiving the two delta coded signals to be added and generating the output signal of said match channel means.
Claim 10
Dependent Claim
41 words
An adding circuit as claimed in claim 2 in which the output device is an OR gate connected to the output of the mismatch channel means and the output of the match channel means and generating the output delta coded signal.
References Cited (Backward Citations)
US3666890A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |