US3763361A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computing circuits for the calculation of the standard deviation of an input signal
Assignee: TELOMEX GROUP Ltd
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Filing: 1971-03-08
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Granted: 1973-10-02
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Expires: 1991-03-08
Abstract
Abstract A computing circuit for computing the standard deviation of a group of signals such as signals representing the weights of a series of articles during production or packaging is disclosed. The signals are fed into a network which splits the signals up into sub-groups and the range of each sub-group is determined. A signal representing a predetermined proportion of the range is fed to an integrating circuit such that the sum of these portions represents the division of the mean of the ranges of the subgroups by a factor known as the ''''mean range factor'''' the size of this factor varying with the number of signals in each sub-group. A method of determining the mean of the values of the signals using the same method is disclosed. In this method the deviation of each signal from an assumed mean is determined and divided by a signal representative of the number of signals in the group to provide an increment signal. The increment signals are then summed to provide a signal representing the true mean.
Inventors
- 👤 E Smart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:09
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/48; G06G7/52; G06G7/12; G06G7/18; G06G7/20
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
309 words
Apparatus for computing the standard deviation of a group of input signals, comprising an input line for receiving said input signals of said group, a plurality of temporary storage means, routing means interconnecting said input line and said temporary storage means, said routing means including a controllable switch in the input line to each said temporary storage means, and operating to direct said input signals to respective ones of said temporary storage means to form a plurality of subgroups of said input signals, each said sub-group containing a predetermined number of said input signals, timing logic means producing first timing signals to control the opening of said controllable switches, a timing signal generator connected to provide timing signals to said timing logic means, range determining means connected to said temporary storage means for determining the statistical range of each said subgroup of said input signals, said range determining means producing an output signal representing said statistical range of each said sub-group of said input signals, scaling means connected to the output of said range determining means, said scaling means producing an output signal therefrom representing a predetermined proportion of the output signal from said range determining means determined with reference to the mean range factor for sub-groups containing said predetermined number of signals, and integrator means for summing said signals from said scaling means to produce an output signal representing a said predetermined proportion of the sum of said statistical ranges of said plurality of sub-groups of said group of input signals, said output signal from said integrator means representing the standard deviation of said group of input signals., and means interconnecting said logic circuit means and said integrator means whereby said logic circuit means produces second timing signals to said integrator means at predetermined times with reference to said first timing signals periodically to enable said integrator means.
Claim 2
Dependent Claim
309 words
Apparatus for computing the standard deviation of a group of input signals, comprising an input line for receiving said input signals of said group, a plurality of temporary storage means, routing means interconnecting said input line and said temporary storage means, said routing means including a controllable switch in the input line to each said temporary storage means, and operating to direct said input signals to respective ones of said temporary storage means to form a plurality of subgroups of said input signals, each said sub-group containing a predetermined number of said input signals, timing logic means producing first timing signals to control the opening of said controllable switches, a timing signal generator connected to provide timing signals to said timing logic means, range determining means connected to said temporary storage means for determining the statistical range of each said subgroup of said input signals, said range determining means producing an output signal representing said statistical range of each said sub-group of said input signals, scaling means connected to the output of said range determining means, said scaling means producing an output signal therefrom representing a predetermined proportion of the output signal from said range determining means determined with reference to the mean range factor for sub-groups containing said predetermined number of signals, and integrator means for summing said signals from said scaling means to produce an output signal representing a said predetermined proportion of the sum of said statistical ranges of said plurality of sub-groups of said group of input signals, said output signal from said integrator means representing the standard deviation of said group of input signals., and means interconnecting said logic circuit means and said integrator means whereby said logic circuit means produces second timing signals to said integrator means at predetermined times with reference to said first timing signals periodically to enable said integrator means.
Claim 3
Dependent Claim
24 words
The apparatus of claim 1 wherein there are two said storage means and said sub-groups of said input signals comprise two of said signals.
Claim 4
Dependent Claim
32 words
The apparatus of claim 2 wherein said range determining means comprises a difference circuit the output from which represents the difference between the two said signals of each said sub-group in turn.
Claim 5
Dependent Claim
17 words
The apparatus of claim 1 wherein there are provided means displaying the output of said integrator means.
Claim 6
Dependent Claim
18 words
The apparatus of claim 1 wherein there are provided means for recording the output of said integrator means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-01 | 1977-04-02 | 1977-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-01 | 1981-04-02 | 1981-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-01 | 1985-04-02 | 1985-10-02 | $7700.00 | Window Closed / Lapsed |