Output control logic for a code reading system

Claim 2

In a data processing system capable of developing characters of data information in a most significant or least significant order and providing said characters of data information in said most significant order regardless of the order in which said characters of data information are developed, output logic comprising: means for providing a direction signal capable of having a first or a second value, said values respectively being indicative of whether the characters of data information are developed in said most significant order or said least significant order; an M equal to or greater than one character recirculating memory in which a plurality of multibit characters of said data information and at least one multibit character of control information are stored, said memory having an output to which is cyclically applied said control character, followed by said data characters, said data characters being applied to said output most significant character first when said direction signal is said first value and least significant character first when said direction signal is said second value; index register means capable of being forced to an initial count of the number of characters applied to said memory output from the time said control character is applied thereto until after the time said most significant character is applied thereto, said index register on command of a command signal being incremented in the event said direction signal is said first value and being decremented in the event said direction signal is said second value; count forcing means responsive to the application thereto of said control character and said direction signal for forcing the count of said index register means to the initial count thereof; position counter means for cyclically counting from one to M by incrementing the count thereof once each time a character is applied to said output, the count of said position counter means being one during the time said control character is being applied to said output; comparator means for providing a compare signal whenever the counts of said index register means and said position counter means are equal, the first occurring one of said compare signals occurring when the most significant data characer is available at said output of said memory and successively occurring ones of said compare signals occur when each of said data characters stored in said memory are available at said output of said memory in decreasing significance order; and means for providing said command signal after each time said compare signal occurs.

Claim 3

The invention to claim 1: wherein said combination further includes limit register means capable of being forced to an initial count equal to the number of characters applied to said output from the time said control character is applied thereto until after the time said least significant character is applied thereto, and second comparator means for providing a second compare signal whenever the counts of said limit register means and said index register means are equal, said second compare signal occurring after the time said least significant data character stored in said memory is available at said output of said memory; wherein said command signal providing means provides said command signal until said second compare signal occurs; and wherein said count forcing means is also responsive to the application thereto of said control character and said direction signal for forcing the count of said limit register means to the initial count thereof.

Claim 4

The invention according to claim 2 wherein said memory is a shift register and said control character and said data characters are applied serially to said output.

Claim 5

The invention according to claim 2: wherein said control character includes at least one bit manifesting a size code number which is related to the number of information characters stored in said memory; and wherein said count forcing means is responsive to the application thereto of said size code bits and said direction signal for forcing the counts of said index register means and said limit register means to the initial counts thereof.

Claim 6

The invention according to claim 4: wherein said memory is a shift register, and said control character and data characters are applied serially to said output, an output signal thereby being provided which manifests the bits stored in said memory, said count forcing means being responsive to the size code bits manifested by said output signal.

Claim 7

The invention according to claim 5: wherein said count forcing means responds to said direction signal having said first value by forcing the count of said index register to a fixed number equal to the number of control characters applied to said output prior to the application thereto of said most significant data character and by forcing the count of said limit register means to a count related to said size code number; and wherein said count forcing means responds to said direction signal having said second value by forcing the count of said index register to a count related to said size code number and by forcing the count of said limit register to a fixed number equal to the number of control characters applied to said output prior to the application thereto of said least significant data character.

Claim 8

The invention according to claim 6: wherein said combination further includes output register means for storing a selected character of said output signal which is applied thereto, said selected character being the one immediately following the occurrence of said first compare signal, said character being provided in a first bit order of significance in the event said direction signal is said first value and in the opposite bit order of significance in the event said direction signal is said second value, said output register means including logic means for causing said selected character to be provided as an output register signal in a given bit order of significance regardless of said direction signal value.

Claim 9

The invention according to claim 7: wherein said output register is a right-left shift register which provides said output register signal by right-shifting the selected character stored thereby in the event said direction signal is one value and by left-shifting the selected character stored thereby in the event said direction signal is the other value.

Claim 10

Control logic for causing the data stored in an M equal to or greater than one character recirculating memory to be transferred as a memory output signal through an output thereof to a utilization device, said memory storing a plurality of multibit data characters, at least one front control multibit character and at least one back control multibit character, each of said one front and one back control characters including a multibit size code manifesting a number related to the number data characters, said plurality of multibit data characters including a most significant character and a least significant character with a given number, including zero, of characters decreasing in significance order therebetween, the arrangement of said characters in said memory being in accordance with the value of a direction signal such that for a first direction signal value, the characters are arranged so that they are transferred through said memory output in the order of said one front control character, most significant to least significant data characters, and said one back control character, and for a second direction signal value, the characters are transferred through said memory output in the order of said one back control character, least significaNt to most significant data character, and said one front control character, the bit order of each data character being least significant to most significant bit for one direction signal value and most significant to least significant bit for the other direction signal value, said control logic comprising: output buffer means responsive to said memory output signal, a first control signal, a second control signal, and a third control signal, for storing the one of the characters represented by said memory output signal provided during the time said first control signal is provided, and for providing in response to one of said second and third control signals an output buffer signal manifesting the character stored thereby, said output buffer signal manifesting a stored data character in the same predetermined significant bit order irrespective of the bit order of how that character is represented by the memory output signal applied to said output buffer means; first counter means for incrementing its count by one each time one character of data stored in said memory is recirculated through said memory output, the count of said first counter being one during the time said one front control character is recirculated through said memory output in the event said direction signal has said first value, or during the time said one back control character is recirculated through said output in the event said direction signal has said second value; first register means responsive to the size code manifested by said output buffer signal for being set to the count of said first counter means at the time the most significant data character is recirculated through said memory output; second counter means, capable of being incremented or decremented, after being set to the count of said first counter means at the time the most significant data character is recirculated through said memory output, the count of said second counter being incremented after said output buffer signal is provided in the event said direction signal is said first value and being decremented after said output buffer signal is provided in the event said direction signal is said second value; first comparing means for providing said first control signal when the counts of said first counter means and said second counter means are equal; second comparing means for providing a fourth control signal whenever the counts of said second counter means and said first register means are equal; and control signal providing means responsive to said direction signal, said first control signal, and said fourth control signal for providing said second control signal after each first control signal occurs so long as said fourth control signal has not occurred in the event said direction signal has said first value, and for providing said third control signal after each first control signal occurs so long as said fourth control signal had not occurred in the event said direction signal has said second value.

Claim 11

Control logic for causing the data stored in an M equal to or greater than one character recirculating memory to be transferred as a memory output signal through an output thereof to a utilization device, said memory storing a plurality of multibit data characters, at least one front control multibit character and at least one back control multibit character, each of said one front and one back control characters including a multibit size code manifesting a number related to the number data characters, said plurality of multibit data characters including a most significant character and a least significant character with a given number, including zero, of characters decreasing in significance order therebetween, the arrangement of said characters in said memory being in accordance with the value of a direction signal such that for a first direction signal value, the characters are arranged so that they are transferred through said memory output in the order of said one front control character, most significant to least significant data characters, and said one back control character, and for a second direction signal value, the characters are transferred through said memory output in the order of said one back control character, least significaNt to most significant data character, and said one front control character, the bit order of each data character being least significant to most significant bit for one direction signal value and most significant to least significant bit for the other direction signal value, said control logic comprising: output buffer means responsive to said memory output signal, a first control signal, a second control signal, and a third control signal, for storing the one of the characters represented by said memory output signal provided during the time said first control signal is provided, and for providing in response to one of said second and third control signals an output buffer signal manifesting the character stored thereby, said output buffer signal manifesting a stored data character in the same predetermined significant bit order irrespective of the bit order of how that character is represented by the memory output signal applied to said output buffer means; first counter means for incrementing its count by one each time one character of data stored in said memory is recirculated through said memory output, the count of said first counter being one during the time said one front control character is recirculated through said memory output in the event said direction signal has said first value, or during the time said one back control character is recirculated through said output in the event said direction signal has said second value; first register means responsive to the size code manifested by said output buffer signal for being set to the count of said first counter means at the time the most significant data character is recirculated through said memory output; second counter means, capable of being incremented or decremented, after being set to the count of said first counter means at the time the most significant data character is recirculated through said memory output, the count of said second counter being incremented after said output buffer signal is provided in the event said direction signal is said first value and being decremented after said output buffer signal is provided in the event said direction signal is said second value; first comparing means for providing said first control signal when the counts of said first counter means and said second counter means are equal; second comparing means for providing a fourth control signal whenever the counts of said second counter means and said first register means are equal; and control signal providing means responsive to said direction signal, said first control signal, and said fourth control signal for providing said second control signal after each first control signal occurs so long as said fourth control signal has not occurred in the event said direction signal has said first value, and for providing said third control signal after each first control signal occurs so long as said fourth control signal had not occurred in the event said direction signal has said second value.

Claim 12

The invention according to claim 9: wherein said output buffer means includes a shift register responsive to said second control signal for shifting in one direction and responsive to said third control signal for shifting in the other direction.

Claim 13

The invention according to claim 9: wherein said data characters stored in said output buffer means are stored in complemented form in the event said direction signal is said second value; and wherein said output buffer means in responding to said third control signal includes means for providing said output buffer signal as manifesting the complement of the character stored thereby.

Claim 14

The invention according to claim 11: wherein the number manifested by said size code is equal to the number of front control characters plus the number of data characters stored in said memory; and wherein said first register means includes means for setting the count of said first register means to said size code number in the Event said direction signal is said first value in response to said output buffer signal manifesting said first control character stored thereby.