US3760127A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for the remote supervision of multichannel pcm repeaters
Assignee: Italtel SpA
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Filing: 1971-11-15
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Granted: 1973-09-18
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Expires: 1991-11-15
Abstract
Abstract Groups of repeaters in n cascaded repeating stations of a multichannel PCM transmission system are individually tested via a supervisory d-c circuit by different interrogation codes emitted from one terminal of the transmission path, each interrogation code including a train of equispaced address pulses whose number (ranging from 1 through n) identifies a selected station. A control unit at the code-emitting terminal comprises a binary counter manually adjustable to count a selected number of address pulses followed in the code by a pulse interval long enough to allow for the generation of a one-pulse reply code at the station so addressed, a similar counter at that station enabling a pulse generator to produce the reply code in the presence of consent signals from a processor receiving the outputs of m monitoring circuits connected across as many repeaters in each station. The processor is divided into two halves each serving a subgroup of m/2 repeaters used to transmit in one or the other direction.
Inventors
- 👤 R Camiciottoli
- 👤 G Grossi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:53
CPC Classifications
H; H04; H04B; H04B17/00; H04B17/40; H04B17/401; H04B17/406
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
304 words
A system for the remote supervision of a series of n repeating stations inserted in a PCM signal path with m channels, each station containing m repeaters individually assigned to said channels, comprising: a service line extending along said path; a control unit connected to said line for transmitting interrogation codes thereover to said stations during successive test cycles and receiving reply codes therefrom indicative of the performance of the repeaters of each station, said control unit including a code generator selectively settable to produce n different interrogation codes respectively addressed to said stations; a group of m monitoring circuits respectively connected across the m repeaters of each station for generating error signals upon improper performance of any repeater; a processor at each station including discriminator means connected to said line for generating an enabling signal upon detecting an interrogation code addressed to the respective station, said processor further including responder means connected to said discriminator means and to said monitoring circuits for generating a reply code in the presence of said enabling signal and in the absence of any error signal; and indicator means in said control unit for registering the nonarrival of a reply code in a succession of test cycles; each of said monitoring circuits comprising a push-pull amplifier connected across the associated repeater for comparing message pulses concurrently present in the input and in the output of the latter, a first integrator connected to said amplifier for generating an error signal in response to a succession of unbalance pulses indicating a mismatch, and a second integrator connector to the repeater input for generating an idleness signal in response to prolonged absence of incoming message pulses, said responder means being connected to both said integrators for generating and reply code only in the absence of both error signals and idleness signals.
Claim 2
Independent Claim
304 words
A system for the remote supervision of a series of n repeating stations inserted in a PCM signal path with m channels, each station containing m repeaters individually assigned to said channels, comprising: a service line extending along said path; a control unit connected to said line for transmitting interrogation codes thereover to said stations during successive test cycles and receiving reply codes therefrom indicative of the performance of the repeaters of each station, said control unit including a code generator selectively settable to produce n different interrogation codes respectively addressed to said stations; a group of m monitoring circuits respectively connected across the m repeaters of each station for generating error signals upon improper performance of any repeater; a processor at each station including discriminator means connected to said line for generating an enabling signal upon detecting an interrogation code addressed to the respective station, said processor further including responder means connected to said discriminator means and to said monitoring circuits for generating a reply code in the presence of said enabling signal and in the absence of any error signal; and indicator means in said control unit for registering the nonarrival of a reply code in a succession of test cycles; each of said monitoring circuits comprising a push-pull amplifier connected across the associated repeater for comparing message pulses concurrently present in the input and in the output of the latter, a first integrator connected to said amplifier for generating an error signal in response to a succession of unbalance pulses indicating a mismatch, and a second integrator connector to the repeater input for generating an idleness signal in response to prolonged absence of incoming message pulses, said responder means being connected to both said integrators for generating and reply code only in the absence of both error signals and idleness signals.
Claim 3
Dependent Claim
36 words
A system as defined in claim 1 wherein each monitoring circuit includes a supply of operating current for said processor and logic circuits responsive to a succession or error signals for cutting off said operating current.
Claim 4
Dependent Claim
59 words
A system as defined in claim 1 wherein said push-pull amplifier comprises two transistor stages and a coupling transformer with a secondary winding connected across the inputs of said stages, said monitoring circuit further including bistable means inserted between said push-pull amplifier and said first integrator, said second integrator being connected to the output of one of said stages.
Claim 5
Dependent Claim
21 words
A system as defined in claim 3, further comprising a pulse-broadening circuit inserted between said bistable means and said first integrator.
Claim 6
Dependent Claim
101 words
A system as defined in claim 1 wherein m is an even number, said repeaters and monitoring circuits being divided into two equal subgroups serving for the transmission of PCM messages over said path in two directions, said discriminating means being provided with two outputs for generating two separate enabling signals in response to interrogation codes identifying either of said subgroups, said processor being divided into two halves each connected to a respective subgroup of monitoring circuits, said responder means having two inputs each connected to a respective output of said discriminating means and to a respective half of said processor.
Claim 7
Dependent Claim
214 words
A system as defined in claim 1 wherein said control unit comprises a source of clock pulses, a first pulse counter connected to said source, selector means for setting said first pulse counter to produce a stop signal upon its count reaching a value assigned to a selected repeating station, first transceiver means on said line switchable between a transmitting condition and a receiving condition, gating means inserted between said source and said first transceiver means for converting said clock pulses into address pulses, first timing means responsive to said stop signal for operating said gating means to terminate the transmission of said address pulses upon said counter reaching said assigned value and to resume such transmission after a predetermined recoveRy interval, and second timing means responsive to said stop signal for establishing said receiving condition during an answering-back period constituting a predetermined fraction of said recovery interval; said discriminator means comprising second transceiver means on said line responsive to a line voltage indicative of the condition of said first transceiver means for assuming a complementary condition, and a second pulse counter connected to said second transceiver means for receiving said address pulses therefrom and for generating said enabling signal upon termination of said address pulses on a count individual to the respective station.
Claim 8
Independent Claim
409 words
A system for the remote supervision of a series of a repeating stations inserted in a PCM signal path with m channels, each station containing m repeaters individually assigned to said channels, comprising: a service line extending along said path; a control unit connected to said line for transmitting interrogation codes thereover to said stations during successive test cycles and receiving reply codes therefrom indicative of the performance of the repeaters of each station, said control unit including a code generator selectively settable to produce n different interrogation codes respectively addressed to said stations; a group of m monitoring circuits respectively connected across the m repeaters of each station for generating error signals upon improper performance of any repeater; a processor at each station including discriminator means connected to said line for generating an enabling signal upon detecting an interrogation code addressed to the respective station, said processor further including responder means connected to said discriminator means and to said monitoring circuits for generating a reply code in the presence of said enabling signal and in the absence of any error signal; and indicator means in said control unit for registering the nonarrival of a reply code in a succession of test cycles; said control unit comprising a source of clock pulses, a first pulse counter connected to said source, selector means for setting said first pulse counter to produce a stop signal upon its count reaching a value assigned to a selected repeating station, first transceiver means on said line switchable between a transmitting condition and a receiving condition, gating means inserted between said source and said first transceiver means for converting said clock pulses into address pulses, first timing means responsive to said stop signal for operating said gating means to terminate the transmission of said address pulses upon said count reaching said assigned value and to resume such transmission after a predetermined recovery interval, and second timing means responsive to said stop signal for establishing said receiving condition during an answer-back period constituting a predetermined fraction of said recovery interval; said discriminator means comprising second transceiver means on said line responsive to a line voltage indicative of the condition of said first transceiver means for assuming a complementary condition, and a second pulse counter connected to said second transceiver means for receiving said address pulses therefrom and for generating said enabling signal upon termination of said address pulses on a count individual to the respective station.
Claim 9
Independent Claim
409 words
A system for the remote supervision of a series of a repeating stations inserted in a PCM signal path with m channels, each station containing m repeaters individually assigned to said channels, comprising: a service line extending along said path; a control unit connected to said line for transmitting interrogation codes thereover to said stations during successive test cycles and receiving reply codes therefrom indicative of the performance of the repeaters of each station, said control unit including a code generator selectively settable to produce n different interrogation codes respectively addressed to said stations; a group of m monitoring circuits respectively connected across the m repeaters of each station for generating error signals upon improper performance of any repeater; a processor at each station including discriminator means connected to said line for generating an enabling signal upon detecting an interrogation code addressed to the respective station, said processor further including responder means connected to said discriminator means and to said monitoring circuits for generating a reply code in the presence of said enabling signal and in the absence of any error signal; and indicator means in said control unit for registering the nonarrival of a reply code in a succession of test cycles; said control unit comprising a source of clock pulses, a first pulse counter connected to said source, selector means for setting said first pulse counter to produce a stop signal upon its count reaching a value assigned to a selected repeating station, first transceiver means on said line switchable between a transmitting condition and a receiving condition, gating means inserted between said source and said first transceiver means for converting said clock pulses into address pulses, first timing means responsive to said stop signal for operating said gating means to terminate the transmission of said address pulses upon said count reaching said assigned value and to resume such transmission after a predetermined recovery interval, and second timing means responsive to said stop signal for establishing said receiving condition during an answer-back period constituting a predetermined fraction of said recovery interval; said discriminator means comprising second transceiver means on said line responsive to a line voltage indicative of the condition of said first transceiver means for assuming a complementary condition, and a second pulse counter connected to said second transceiver means for receiving said address pulses therefrom and for generating said enabling signal upon termination of said address pulses on a count individual to the respective station.
Claim 10
Dependent Claim
130 words
A system as defined in claim 7 wherein at least one of said transceiver means comprises a first transistor and a second transistor in series, said first transistor having a first output connection, a third transistor having a second output lead, said first and third transistors being provided with a common input lead, said second transistor having an input connection extending to said second output lead, and biasing means in said input connection for establishing a receiving condition upon energization of said common input lead with saturation of said first and thrid transistors whereby pulses arriving over said second output lead are reProduced on said first output lead, pulsing of said common input lead causing intermittent energization of said second output lead to the exclusion of said first output lead.
Claim 11
Dependent Claim
66 words
A system as defined in claim 7 wherein said control unit further comprises a signal evaluation connected to said first transceiver means for receiving said reply codes therefrom, said signal evaluator being further connected to said second timing means for enablement during said answer-back period and to said indicator means for actuating same upon the nonarrival of a reply code in a succession of answer-back periods.
Claim 12
Dependent Claim
30 words
A system as defined in claim 9 wherein said signal evaluator includes a flip-flop connected to be reset by said stop signal and to be set by said response code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-17 | 1977-03-19 | 1977-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-17 | 1981-03-19 | 1981-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-17 | 1985-03-19 | 1985-09-18 | $7700.00 | Window Closed / Lapsed |