Sender pulse timing control

Claim 1

In a communication switching system having a plurality of junctors, each including a line terminal for connection to a communication line to send call signals; register-sender apparatus comprising a memory and logic circuits shared on a time division multiplex basis, said memory having sets of storage elements, a plurality of registers individually associated with said junctors, each register comprising a block with a given number of said sets including at least one sender control set; sender means connected at least during a sending portion of a call to the junctor line terminal, the sender means including means for producing pulses with alternate on and off intervals at the junctor line terminal; a multiplex arrangement comprising multiplex circuits coupling the logic circuits to the junctors and sender means, read and write circuits coupling the logic circuits to the memory, and a source of cyclically recurring pulses; with each register having an individual pulse time slot occurring once per cycle during which the logic circuits are effectively coupled via the multiplex circuits to the associated junctor and the sender means connected to its line terminal, wherein the information in the corresponding memory block is read via said read circuits, selectively modified, and written back into the block via said write circuits; whereby the logic circuits are common and used for each register only during its time slot; wherein the sender control set of each register includes a timer store, a digit store, and an on-off control store; wherein the logic circuits iNclude a timing counter connected to act on timing information read from the timer store and with its output written into the timer store, with means to set the timing information to a starting value and means to increment the value at given periodic intervals, and the logic circuits including means to decode the timing information value to indicate elapsed time since last set to the starting value; wherein the information in said on-off control store has alternate ''''on'''' and ''''off'''' values; and the logic circuits include means responsive to coincidence of given sending conditions, an ''''off'''' value of the on-off control information, and a first decoded value of the timing information to write the ''''on'''' value in the on-off control store and the starting value in the timer store; and means responsive to coincidence of said given sending conditions, an ''''on'''' value of the on-off control information, and a second decoded value of the timing information to write the ''''off'''' value in the on-off control store and the starting value in the timer store; means in the logic circuits connected to receive the information read from the on-off control store to control a logic-circuit on-off storage means so that its state corresponds to the value of the on-off control information; wherein said multiplex circuits include multiplex on-off storage means individual to the sender means, and means connected to the output of the logic-circuit on-off storage means to control the multiplex on-off storage means of each sender means during its time slot so that its state corresponds thereto and remains in that state during the remainder of that cycle; and a connection from the output of each multiplex on-off storage means to the associated sender means to control it to produce corresponding on nd off intervals.