Umbers b to a base of b or vice versa circuit for the parallel conversion of numbers a into a base a into n

Claim 1

Apparatus for the parallel conversion of numbers D to a base d into corresponding numbers Z to a base z and vice versa, comprising: first and second M X N matrices having electrical signals representing the digits of a number A applied to the line inputs thereof and electrical signals representing the digits of a number B applied to the column inputs thereof, said matrices comprising a plurality of substantially similar logic circuit elements which process electrical signals representing the digits of the numbers to be converted, a digit Ai of the number A being applied to a line input of one of said logic circuit elements, a digit Bi of the number B being applied to a column input of one of said logic circuit elements; said logic circuit elements comprising means generating a digit Bi 1 in the column outputs of said elements, where Bi 1 (Bi . a + Ai)mod b and represents the remainder of the division of Bi . + Ai by b, and further means generating a digit Ai 1 at the line outputs of said elements, where Ai 1 (1/b) (Bi 54 . a + Ai - Bi 1) and represents the quotient of said division; wherein the electrical signals at the column outputs of said matrices represent a number R (B . am + A)mod b representing the remainder of the division of B . am + A by bn and the electrical signal at the line outputs of said matrices represent a number Q (1/bn) (B . am + A - R), representing the quotient of said division; and further wherein said first matrix comprises logic elements having means to divide by the factor z (d a, z b) and said second matrix comprises logic elements having means to divide by the factor d (z a, d b).

Claim 3

An apparatus for the parallel conversion of numbers D to a base d into corresponding numbers Z to a base z including first and second M X N matrices, each matrix comprising a plurality of substantially similar logic circuit elements which process electrical signals representing the digits of the numbers to be converted, said first matrix comprising logic elements having means to divide by the factor z and said second matrix comprising logic elements having means to divide by the factor d, a digit Ai of a number A being applied to a row input of one of said logic circuit elements and a digit Bi of a number B being applied to a column input of one of said logic circuit elements, said logic circuit elements further comprising means generating a digit Bi 1 in the column outputs of said elements, where Bi 1 (Bi . a + Ai)mod b and represents the remainder of the division of Bi . a + Ai by b, and further means generating a digit Ai 1 at the row outputs of said elements, where Ai 1 (1/b) (Bi . a + Ai - Bi 1) and represents the quotient of said division, wherein the electrical signals at the column outputs of said matrices represent a number R (B . am + A)mod b representing the remainder of the division of B . am + A by bn and the electrical signal at the row outputs of said matrices represent a number Q (1/bn) (B . am + A - R), representing the quotient of said division, wherein a zero value is applied to the column inputs of the first matrix and to the row inputs of the second matrix; the integer part of the number to be converted is applied to the row inputs of the first matrix, such that the most significant digit of the integer part is applied to the row adjacent to the column inputs of the first matrix; and the fractional part of the number to be converted is applied to the column inputs of the second matrix, such that the most significant digit of the fractional part is applied to the column adjacent to the row outputs of the second matrix.

Claim 4

An apparatus for the parallel conversion of numbers D to a base d into corresponding numbers Z to a base z including first and second M X N matrices, each matrix comprising a plurality of substantially similar logic circuit elements which process electrical signals representing the digits of the numbers to be converted, said first matrix comprising logic elements having means to divide by the factor z and said second matrix comprising logic elements having means to divide by the factor d, a digit Ai of a number A being applied to a row input of one of said logic circuit elements and a digit Bi of a number B being applied to a column input of one of said logic circuit elements, said logic circuit elements further comprising means generating a digit Bi 1 in the column outputs of said elements, where Bi 1 (Bi . a + Ai)mod b and represents the remainder of the division of Bi . a + Ai by b, and further means generating a digit Ai 1 at the row outputs of said elements, where Ai 1 (1/b) (Bi . a + Ai - Bi 1) and represents the quotient of said division, wherein the electrical signals at the column outputs of said matrices represent a number R (B . am + A)mod b representing the remainder of the division of B . am + A by bn and the electrical signal at the row outputs of said matrices represent a number Q (1/bn) (B . am + A - R), representing the quotient of said division, wherein a zero value is applied to the column inputs of the first matrix and to the row inputs of the second matrix; the integer part of the number to be converted is applied to the row inputs of the first matrix, such that the most significant digit of the integer part is applied to the row adjacent to the column inputs of the first matrix; and the fractional part of the number to be converted is applied to the column inputs of the second matrix, such that the most significant digit of the fractional part is applied to the column adjacent to the row outputs of the second matrix.

Claim 5

An apparatus for the parallel conversion of numbers Z to a base z into corresponding numbers D to a base d including first and second M X N matrices, each matrix comprising a plurality of substantially similar logic circuit elements which process electrical signals representing the digits of the numbers to be converted, said first matrix comprising logic elements having means to divide by the factor z and said second matrix comprising logic elements having means to divide by thE factor d, a digit Ai of a number A being applied to a row input of one of said logic circuit elements and a digit Bi of a number B being applied to a column input of one of said logic circuit elements, said logic circuit elements further comprising means generating a digit Bi 1 in the column outputs of said elements, where Bi 1 (Bi . a + Ai)mod b and represents the remainder of the division of Bi . a + Ai by b, and further means generating a digit Ai 1 at the row outputs of said elements, where Ai 1 1/b (Bi . a + Ai - Bi 1) and represents the quotient of said division, wherein the electrical signals at the column outputs of said matrices represent a number R (B . am + A)mod b representing the remainder of the division of B . am + A by bn and the electrical signal at the row outputs of said matrices represent a number Q (1/bn) (B . am + A - R), representing the quotient of said division, wherein a zero value is applied to the column inputs of the second matrix and to the row inputs of the first matrix; the integer part of the number to be converted is applied to the row inputs of the second matrix such that the most significant digit of the integer part is applied to the row adjacent to the column inputs of the second matrix; and the fractional part of the number to be converted is applied to the column inputs of the first matrix, such that the most significant digit of the fractional part is applied to the column adjacent to the row input.

Claim 6

An apparatus for the parallel conversion of numbers Z to a base z into corresponding numbers D to a base d including first and second M X N matrices, each matrix comprising a plurality of substantially similar logic circuit elements which process electrical signals representing the digits of the numbers to be converted, said first matrix comprising logic elements having means to divide by the factor z and said second matrix comprising logic elements having means to divide by thE factor d, a digit Ai of a number A being applied to a row input of one of said logic circuit elements and a digit Bi of a number B being applied to a column input of one of said logic circuit elements, said logic circuit elements further comprising means generating a digit Bi 1 in the column outputs of said elements, where Bi 1 (Bi . a + Ai)mod b and represents the remainder of the division of Bi . a + Ai by b, and further means generating a digit Ai 1 at the row outputs of said elements, where Ai 1 1/b (Bi . a + Ai - Bi 1) and represents the quotient of said division, wherein the electrical signals at the column outputs of said matrices represent a number R (B . am + A)mod b representing the remainder of the division of B . am + A by bn and the electrical signal at the row outputs of said matrices represent a number Q (1/bn) (B . am + A - R), representing the quotient of said division, wherein a zero value is applied to the column inputs of the second matrix and to the row inputs of the first matrix; the integer part of the number to be converted is applied to the row inputs of the second matrix such that the most significant digit of the integer part is applied to the row adjacent to the column inputs of the second matrix; and the fractional part of the number to be converted is applied to the column inputs of the first matrix, such that the most significant digit of the fractional part is applied to the column adjacent to the row input.