US3757940A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory system having two clock pulse frequencies
Assignee: OI Glass Inc
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Filing: 1972-06-19
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Granted: 1973-09-11
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Expires: 1992-06-19
Abstract
Abstract A series connected dual memory system in which the clocking frequency of one memory is independent of the clocking frequency of the other memory. This system is designed to store and shift defective article information generated by an article inspection machine. The machine removes articles from a continually moving conveyor, indexes the articles one at a time through a series of inspection stations, generates a defect signal if an article fails to pass any one of the inspections, and returns all articles to the conveyor. A first memory stores defective article information. This information is shifted in the memory in synchronism with the index of the article through the inspection machine by a clock pulse at a frequency proportional to the index speed. Any defective article information is transferred into a second memory as the article to which the information pertains is replaced on the conveyor. As the article is moved away from the inspection machine, the information is shifted in the second memory in synchronism with the speed of the article by a clock pulse at a frequency proportional to the speed of the conveyor. When the information in the second memory reaches a rejection station downstream of the inspection machine, the rejection station is activated to remove the article from the conveyor.
Inventors
- 👤 D Damm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:10
CPC Classifications
B; B07; B07C; B07C5/00; B07C5/36; B07C5/361
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
332 words
Apparatus for inspecting and segregating articles comprising, in combination: conveyor means for moving said articles in single file; an article inspection machine located adjacent said conveyor means for receiving said articles one at a time therefrom, serially indexing said articles through a plurality of inspection stations, and releasing inspected articles to said conveyor means; an article defect logic and detection means connected to said plurality of inspection stations for generating one or more output signals if an article is defective in one or more aspects, said article defect logic and detection means having a plurality of output leads at least equal in number to the number of said inspection stations; a rejection means adjacent said conveyor means, downstream of said inspection machine, for removing defective articles from said conveyor means; first clock means for generating a series of machine clock pulses in synchronism with the index cycle of said inspection machine; first memory means connected to said article defect logic and detection means and to said first clock means for storing defective article information generated by said article defect logic and detection means and for shifting said information in response to said machine clock pulses of said first clock means in synchronism with the index of said article from inspection station to inspection station; second clock means for generating a series of conveyor clock pulses in synchronism with the speed of travel of said conveyor means, the frequency of said machine clock pulses and said conveyor clock pulses being independent of one another; and second memory means connected to said second clock means, said first memory means and said rejection means for receiving defective article information from said first memory means as said article is released to said conveyor means, for shifting said information in response to said conveyor clock pulses in synchronism with the movement of said article along said conveyor means, and for actuating said rejection means as said article reaches said rejection means to thereby reject a defective article.
Claim 2
Dependent Claim
332 words
Apparatus for inspecting and segregating articles comprising, in combination: conveyor means for moving said articles in single file; an article inspection machine located adjacent said conveyor means for receiving said articles one at a time therefrom, serially indexing said articles through a plurality of inspection stations, and releasing inspected articles to said conveyor means; an article defect logic and detection means connected to said plurality of inspection stations for generating one or more output signals if an article is defective in one or more aspects, said article defect logic and detection means having a plurality of output leads at least equal in number to the number of said inspection stations; a rejection means adjacent said conveyor means, downstream of said inspection machine, for removing defective articles from said conveyor means; first clock means for generating a series of machine clock pulses in synchronism with the index cycle of said inspection machine; first memory means connected to said article defect logic and detection means and to said first clock means for storing defective article information generated by said article defect logic and detection means and for shifting said information in response to said machine clock pulses of said first clock means in synchronism with the index of said article from inspection station to inspection station; second clock means for generating a series of conveyor clock pulses in synchronism with the speed of travel of said conveyor means, the frequency of said machine clock pulses and said conveyor clock pulses being independent of one another; and second memory means connected to said second clock means, said first memory means and said rejection means for receiving defective article information from said first memory means as said article is released to said conveyor means, for shifting said information in response to said conveyor clock pulses in synchronism with the movement of said article along said conveyor means, and for actuating said rejection means as said article reaches said rejection means to thereby reject a defective article.
Claim 3
Dependent Claim
136 words
The apparatus of claim 1, further including: selector means connected to said article defect logic and detection means for choosing one of said inspection stations to provide an output from selector means when a defective article is present at said inspection station; and third memory means connected to said first clock means, said first memory means, said selector means and said second memory means for receiving defective article information from said selector means, for shifting said information in response to said machine clock pulses of said first clock means in synchronism with the index of said defective article from inspection station to inspection station, and for inserting said information in said second memory means in a position leading the position wherein the same information is inserted in said second memory means by said first memory means.
Claim 4
Dependent Claim
288 words
The apparatus of claim 2, wherein said first memory means comprises, in combination: a first plurality of flip-flops connected in series to form a shift register, said plurality of flip-flops being at least equal in number to the number of inspection stations; a second plurality of flip-flops connected in series to form a shift register, said second plurality of flip-flops being at least equal in number to the number of said first plurality of flip-flops; means connected to said first and second plurality of flip-flops for setting an initial condition in all of said first and second plurality of flip-floPs; an article presence switch adjacent said article inspection machine, connected to the first one of said second plurality of flip-flops, for overcoming the initial condition of said first one of said second plurality of flip-flops when an article is present for inspection; a first plurality of independent signal conditioning means, each of said first plurality of signal conditioning means having one input respectively connected to one of said plurality of output leads from said article defect logic and detection means, for resetting said first plurality of flip-flops; means for connecting the output of said first plurality of signal conditioning means respectively to an input of individual ones of said first plurality of flip-flops; and means for connecting the outputs of said second plurality of flip-flops respectively to a second input of each of said first plurality of signal conditioning means, whereby said first plurality of signal conditioning means will reset said one of said first plurality of flip-flops only when a defective article is detected and when said second plurality of flip-flops indicates the presence of an article at the inspection station where the defective article is detected.
Claim 5
Dependent Claim
222 words
The apparatus of claim 3, wherein said third memory means comprises, in combination: a third plurality of flip-flops connected in series to form a shift register, said third plurality of flip-flops being at least equal in number to the number of inspection stations; means connected to said third plurality of flip-flops for setting an initial condition in all of said third plurality of flip-flops; a second plurality of independent signal conditioning means, each of said second plurality of signal conditioning means having one input respectively connected to one of the outputs of said selector means, for resetting said third plurality of flip-flops; means for connecting the output of said second plurality of signal conditioning means respectively to an input of individual ones of said third plurality of flip-flops; and means for connecting the outputs of said second plurality of flip-flops respectively to a second input of each of said second plurality of signal conditioning means, whereby said second plurality of signal conditioning means will reset said one of said third plurality of flip-flops only when a defective article is detected at the inspection station connected to one of said second plurality of signal conditioning means through said selector means and when said second plurality of flip-flops indicates the presence of an article at the inspection station where the defective article is detected.
Claim 6
Dependent Claim
79 words
The apparatus of claim 3, wherein each of said first plurality of signal conditioning means comprises, in combination: a first NAND gate having its input side connected to one of said second plurality of flip-flops; and a second NAND gate having one input connected to the output of said first NAND gate and having a second input connected to said article defect logic and detection means, and having its output connected to one of said first plurality of flip-flops.
Claim 7
Dependent Claim
75 words
The apparatus of claim 4, wherein each of said second plurality of signal conditioning means comprises, in combination: a first NAND gate having its input side connected to one of said second plurality of flip-flops; and a second NAND gate having one input connected to the output of said first NAND gate and having a second input connected to said selector means, and having its output connected to one of said third plurality of flip-flops.
Claim 8
Dependent Claim
200 words
The apparatus of claim 2, wherein said first clock means includes means for generating a signal during the gauging cycle, and said second memory means comprises, in combination: a plurality of flip-flops connected in series to form a shift register; means connected to said plurality of flip-flops for setting an initial condition in all of said flip-flops; signal Conditioning means having one output connected to the first one of said plurality of flip-flops and a second output connectd to a subsequent one of said flip-flops for resetting said first one and said subsequent one of said flip-flops when a signal is presented by said first memory means and said third memory means and when said gauging signal is present or for resetting only said first one of said flip-flops when a signal is presented only by said first memory means and said gauging signal is present; means for connecting the output of said third memory means to a first input of said signal conditioning means; means for connecting said gauging signal to a second input of said signal conditioning means; and means for connecting the output of said first memory means to a third input of said signal conditioning means.
Claim 9
Dependent Claim
221 words
The apparatus of claim 7 wherein said signal conditioning means comprises, in combination: a first NAND gate having its input connected to said first input of said signal conditioning means; a second NAND gate having its input connected to said second input of said signal conditioning means; a third NAND gate having its input connected to said third input of said signal conditioning means; a fourth NAND gate having one input connected to the output of said first NAND gate and having a second input connected to the output of said second NAND gate, and having its output connected to said subsequent one of said plurality of flip-flops; a first delay capacitor connected in circuit between said first NAND gate and said fourth NAND gate for delaying the propagation of a signal from said first NAND gate to said fourth NAND gate; a fifth NAND gate having one input connected to the output of said third NAND gate and having a second input connected to the output of said second NAND gate, and having its output connected to said first one of said plurality of flip-flops; and a second delay capacitor connected in circuit between said third NAND gate and said fifth NAND gate for delaying the propagation of a signal from said third NAND gate to said fifth NAND gate.
Claim 10
Dependent Claim
144 words
The apparatus of claim 1, wherein said first clock means includes: means for generating a signal during the gauging cycle; a first NAND gate connected to said means for generating a signal; a second NAND gate connected to the output of said first NAND gate; a third NAND gate connected to the output of said second NAND gate; a delay capacitor connected in circuit between said second and third NAND gates for delaying the propagation of a signal from said second to said third NAND gate; a fourth NAND gate connected to the output of said third NAND gate and to said means for generating a signal; and a fifth NAND gate connected to the output of said fourth NAND gate, whereby the output of said fifth NAND gate is a machine clock pulse in synchronism with the index cycle of said inspection machine.
Claim 11
Dependent Claim
26 words
The apparatus of claim 1, wherein said second clock means includes a signal generator for generating a signal proportional to the speed of said conveyor means.
Claim 12
Dependent Claim
154 words
The apparatus of claim 10, wherein said conveyor signal generator comprises, in combination: a substantially U-shaped housing mounted adjacent said conveyor means; an opaque code wheel having a plurality of openings extending therethrough, located at a common radial distance from the axis of said code wheel; means for rotatably mounting said code wheel between the legs of said housing with its periphery in contact with said conveyor means, whereby said code wheel will rotate in proportion to the linear travel of said conveyor means; a light source positioned on the interior of one leg of said housing adjacent said disk at substantially the same radius as that of said openings; and a photoelectric sensor positioned on the leg of said housing opposite said light source in alignmenT with said light source, whereby said photoelectric sensor will generate an output signal whenever one of the openings in said code wheel rotates past said light source.
Claim 13
Dependent Claim
146 words
The apparatus of claim 10 wherein said second clock means includes: a signal amplifier connected to said signal generator; a first NAND gate connected to the output of said signal amplifier; a second NAND gate connected to the output of said first NAND gate; a third NAND gate connected to the output of said second NAND gate; a delay capacitor connected in circuit between said second and third NAND gates for delaying the propagation of a signal from said second NAND gate to said third NAND gate; a fourth NAND gate connected to the output of said third NAND gate and to the output of said signal amplifier; and, a fifth NAND gate connected to the output of said fourth NAND gate, whereby the output of said fifth NAND gate is a conveyor clock pulse in synchronism with the speed of travel of said conveyor means.
Claim 14
Dependent Claim
129 words
The apparatus of claim 1, wherein said first clock means includes means for generating a signal during the gauging cycle, and said second memory means comprises, in combination: a plurality of flip-flops connected in series to form a shift register; means connected to said plurality of flip-flops for setting an initial condition in all of said flip-flops; signal conditioning means having its output connected to the first one of said plurality of flip-flops for resetting said flip-flop when a signal is presented by said first memory means and when said gauging signal is present; means for connecting the output of said first memory means to a first input of said signal conditioning means; and means for connecting said gauging signal to a second input of said signal conditioning means.
Claim 15
Dependent Claim
125 words
The apparatus of claim 13 wherein said signal conditioning means comprises, in combination: a first NAND gate having its input connected to said first input of said signal conditioning means; a second NAND gate having its input connected to said second input of said signal conditioning means; a third NAND gate having one input connected to the output of said first NAND gate and having a second input connected to the output of said second NAND gate, and having its output connected to said first one of said plurality of flip-flops; and a delay capacitor connected in circuit between said first NAND gate and said third NAND gate for delaying the propagation of a signal from said first NAND gate to said third NAND gate.
Claim 16
Dependent Claim
290 words
A memory system for an article inspection machine which removes articles one at a time from a continually moving article conveyor, serially indexes the articles through a plurality of inspection stations, and returns inspected articles to said conveyor, and wherein said inspection machine includes article defect logic and detection means having a plurality of output leads for generating a signal if an article is defective in one or more aspects, comprising the combination of: rejection means adjacent said conveyor downstream of said inspection machine for removing defective articles from said conveyor; first clock means for generating a series of machine clock pulses in synchronism with the index cycle of said inspection machine; first memory means connected to said article defect logic and detection means and to said first clock means for storing defective article information generated by said article defect logic and detection means and for shifting said information in response to said machine clock pulses of said first clock means in synchronism with the index of said article from inspection station to inspection station; second clock means for generating a series of conveyor clock pulses in synchronism with the speed of travel of said conveyor, the frequency of said machine clock pulses and said conveyor clock pulses being independent of one another; and second memorY means connected to said second clock means, said first memory means, and said reject means for receiving defective article information from said first memory means as said article is returned to said conveyor, for shifting said information in response to said conveyor clock pulses in synchronism with the movement of said article along said conveyor, and for actuating said rejection means as said article reaches said reject means to thereby reject a defective article.
Claim 17
Dependent Claim
290 words
A memory system for an article inspection machine which removes articles one at a time from a continually moving article conveyor, serially indexes the articles through a plurality of inspection stations, and returns inspected articles to said conveyor, and wherein said inspection machine includes article defect logic and detection means having a plurality of output leads for generating a signal if an article is defective in one or more aspects, comprising the combination of: rejection means adjacent said conveyor downstream of said inspection machine for removing defective articles from said conveyor; first clock means for generating a series of machine clock pulses in synchronism with the index cycle of said inspection machine; first memory means connected to said article defect logic and detection means and to said first clock means for storing defective article information generated by said article defect logic and detection means and for shifting said information in response to said machine clock pulses of said first clock means in synchronism with the index of said article from inspection station to inspection station; second clock means for generating a series of conveyor clock pulses in synchronism with the speed of travel of said conveyor, the frequency of said machine clock pulses and said conveyor clock pulses being independent of one another; and second memorY means connected to said second clock means, said first memory means, and said reject means for receiving defective article information from said first memory means as said article is returned to said conveyor, for shifting said information in response to said conveyor clock pulses in synchronism with the movement of said article along said conveyor, and for actuating said rejection means as said article reaches said reject means to thereby reject a defective article.
Claim 18
Dependent Claim
137 words
The apparatus of claim 15, further including: selector means connected to said article defect logic and detection means for choosing one of said inspection stations to provide an output from said selector meany when a defective article is present at said inspection station; and third memory means connected to said first clock means, said first memory means, said selector means, and said second memory means for receiving defective article information from said selector means, for shifting said information in response to said machine clock pulses of said first clock means in synchronism with the index of said defective article from inspection station to inspection station, and for inserting said information in said second memory means in a position leading the position wherein the same information is inserted in said second memory means by said first memory means.
Claim 19
Dependent Claim
288 words
The apparatus of claim 15, wherein said first memory means comprises, in combination: a first plurality of flip-flops connected in series to form a shift register, said plurality of flip-flops being at least equal in number to the number of inspection stations; a second plurality of flip-flops connected in series to form a shift register, said second plurality of flip-flops being at least equal in number to the number of said first plurality of flip-flops; means connected to said first and second plurality of flip-flops for setting an initial condition in all of said first and second plurality of flip-flops; an article presence switch adjacent said article inspection machine, connected to the first one of said second plurality of flip-flops, for overcoming the initial condition of said first one of said second plurality of flip-flops when an article is present for inspection; a first plurality of independent signal conditioning means, each of said first plurality of signal conditioning means having one input respectively connected to one of said plurality of output leads from said article defect logic and detection means, for resetting said first plurality of flip-flops; means for connecting the output of said first plurality of signal conditioning means respectively to an input of individual ones of said first plurality of flip-flops; and means for connecting the outputs of said second plurality of flip-flops respectively to a second input of each of said first plurality of signal conditioning means, whereby said first plurality of signal conditioning means will reset said one of said first plurality of flip-flops only when a defective article is detected and when said second plurality of flip-flops indicates the presence of an article at the inspection station where the defective article is detected.
Claim 20
Dependent Claim
223 words
The apparatus of claim 17, wherein said third memory means comprises, in combination: a third plurality of flip-flops connected in series to form a shift register, said third plurality of flip-flops being at least equal in number to the number of inspection stations; means connected to said third plurality of flip-flops for setting an initial condition in all of said third plurality of flip-flops; a second plurality of independent signal conditioning means, each of said second plurality of signal conditioning means having one input respectively connected to one of the outputs of said selector means, for resetting said third plurality of flip-flops; means for connecting the output of said second plurality of signal conditioning means respectively to an input of inDividual ones of said third plurality of flip-flops; and means for connecting the outputs of said second plurality of flip-flops respectively to a second input of each of said second plurality of signal conditioning means, whereby said second plurality of signal conditioning means will reset said one of said third plurality of flip-flops only when a defective article is detected at the article inspection station connected to one of said second plurality of signal conditioning means through said selector means and when said second plurality of flip-flops indicates the presence of an article at the inspection station where the defective article is detected.
Claim 21
Dependent Claim
129 words
The apparatus of claim 15, wherein said first clock means includes means for generating a signal during the gauging cycle, and said second memory means comprises, in combination: a plurality of flip-flops connected in series to form a shift register; means connected to said plurality of flip-flops for setting an initial condition in all of said flip-flops; signal conditioning means having its output connected to the first one of said plurality of flip-flops for resetting said flip-flop when a signal is presented by said first memory means and when said gauging signal is present; means for connecting the output of said first memory means to a first input of said signal conditioning means; and means for connecting said gauging signal to a second input of said signal conditioning means.
Claim 22
Dependent Claim
200 words
The apparatus of claim 16, wherein said first clock means includes means for generating a signal during the engaging cycle, and said second memory means comprises, in combination: a plurality of flip-flops connected in series to form a shift register; means connected to said plurality of flip-flops for setting an initial condition in all of said flip-flops; signal conditioning means having one output connected to the first one of said plurality of flip-flops and a second output connected to a subsequent one of said flip-flops for resetting said first one and said subsequent one of said flip-flops when a signal is presented by said first memory means and said third memory means and when said gauging signal is present or for resetting only said first one of said flip-flops when a signal is presented only by said first memory means and said gauging signal is present; means for connecting the output of said third memory means to a first input of said signal conditioning means; means for connecting said gauging signal to a second input of said signal conditioning means; and means for connecting the output of said first memory means to a third input of said signal conditioning means.
Claim 23
Independent Claim
187 words
A method for rejecting a defective article downstream of an inspection machine which receives articles one at a time from a conveyor, inspects said articles one at a time at multiple inspection stations, indexes said articles from station to station, generates a defect signal for a defective article, and returns all articles one at a time to said conveyor, comprising the steps of: loading defective article information relating to a specific defective one of said articles into a first memory means; shifting said information in said first memory means in synchronism with the index of said defective article by said inspection machine; transferring said defective article information into a second memory means from said first memory means as said defective article is returned to said conveyor; shifting said defective article information in said second memory means in synchronism with the movement of said defective article on said conveyor downstream, away from said inspection machine; and rejecting said defective article from a stream of articles on said conveyor in response to the arrival of said defective article information at a rejection means responsive to said defective article information.
Claim 24
Independent Claim
187 words
A method for rejecting a defective article downstream of an inspection machine which receives articles one at a time from a conveyor, inspects said articles one at a time at multiple inspection stations, indexes said articles from station to station, generates a defect signal for a defective article, and returns all articles one at a time to said conveyor, comprising the steps of: loading defective article information relating to a specific defective one of said articles into a first memory means; shifting said information in said first memory means in synchronism with the index of said defective article by said inspection machine; transferring said defective article information into a second memory means from said first memory means as said defective article is returned to said conveyor; shifting said defective article information in said second memory means in synchronism with the movement of said defective article on said conveyor downstream, away from said inspection machine; and rejecting said defective article from a stream of articles on said conveyor in response to the arrival of said defective article information at a rejection means responsive to said defective article information.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-10 | 1977-03-12 | 1977-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-10 | 1981-03-12 | 1981-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-10 | 1985-03-12 | 1985-09-11 | $7700.00 | Window Closed / Lapsed |