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US3757242A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplifier with long term digitally controlled d c clamping

Assignee: Parke Davis and Co LLC
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Filing: 1972-02-08
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Granted: 1973-09-04
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Expires: 1992-02-08
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Abstract

Abstract By way of information and not by way of limitation, a six bit bar code and six clock bars, one clock bar being paired with each bit, are printed on a carton. The bar code positively identifies the article for which the carton is labeled. During a packaging operation the code is scanned and detected and then compared against a reference code identifying the article being placed in the carton. The arrangement of the code bits or code bars relative to the clock bars and to the scanning sequence is such that a complete code is read bit-by-bit into a digital logic circuit only after enabling of the logic circuit by a clock pulse produced in response to the paired clock bar for each bit. This is done by entering the code into a shift register bit-by-bit with register shifting being under the control of the clock bars. If the code read is not true to the reference code, a reject indication is provided or the carton bearing the incorrect code is automatically rejected from the packaging line. Code and clock pulse signals are fed to the register via specially constructed amplifiers whose output levels are clamped by respective control circuits each of which comprise an oscillator, a threshold detector, a counter, and a digital-to-analog convertor. The analog output from the convertor reduces the input signal when the amplifier output goes above the threshold of the detector.

Inventors

  • 👤 K Law
  • 👤 G Brown

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 22:22
CPC Classifications
B; B07; B07C; B07C5/00; B07C5/34; B07C5/3412; H; H03; H03G; H03G3/00; H03G3/20

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 246 words
An amplifier circuit comprising amplifier means having an input circuit adapted to receive an input signal whose envelope is a series of excursions, said envelope excursions being subject to random variations in duration and in pack amplitude in one direction, said excursions further having information thereon represented by amplitude variations in an opposite direction occurring during at least a portion Of each envelope excursion, an output circuit to develop an output signal that is an amplified version of said input signal, and compensation circuit means coupled between said input circuit and said output circuit to maintain peak envelope amplitudes in said output signal at or below a predetermined level, said compensation circuit means comprising threshold circuit means responsive to said output signal to detect deviations therein above said predetermined level and provide a threshold output signal, digital circuit means enabled by said threshold output signal to provide a digital signal representing said output deviation, and digitalto-analog conversion means responsive to said digital signal to provide an analog signal representing said deviation, said analog signal being coupled to said amplifier input circuit so as to compensate said input signal when said output signal exceeds said predetermined level without changing the gain of said amplifier means to thereby cause peak envelope amplitudes of said output signal to be clamped at or below said predetermined level while information variations in said output signal are substantially unchanged as compared to such information variations in said output signal without such compensation.
Claim 2
Dependent Claim 246 words
An amplifier circuit comprising amplifier means having an input circuit adapted to receive an input signal whose envelope is a series of excursions, said envelope excursions being subject to random variations in duration and in pack amplitude in one direction, said excursions further having information thereon represented by amplitude variations in an opposite direction occurring during at least a portion Of each envelope excursion, an output circuit to develop an output signal that is an amplified version of said input signal, and compensation circuit means coupled between said input circuit and said output circuit to maintain peak envelope amplitudes in said output signal at or below a predetermined level, said compensation circuit means comprising threshold circuit means responsive to said output signal to detect deviations therein above said predetermined level and provide a threshold output signal, digital circuit means enabled by said threshold output signal to provide a digital signal representing said output deviation, and digitalto-analog conversion means responsive to said digital signal to provide an analog signal representing said deviation, said analog signal being coupled to said amplifier input circuit so as to compensate said input signal when said output signal exceeds said predetermined level without changing the gain of said amplifier means to thereby cause peak envelope amplitudes of said output signal to be clamped at or below said predetermined level while information variations in said output signal are substantially unchanged as compared to such information variations in said output signal without such compensation.
Claim 3
Dependent Claim 22 words
The amplifier circuit set forth in claim 1 wherein said digital circuit means comprises counting means enabled by said threshold output signal.
Claim 4
Dependent Claim 64 words
The amplifier circuit set forth in claim 2 wherein said digital circuit means further comprises gate means and oscillator means coupled to said counter means via said gate means, said gate means being enabled by said threshold out-put signal to repetitively increment said counter in response to a counting signal from said oscillator means so long as said output signal exceeds said predetermined level.
Claim 5
Dependent Claim 52 words
The amplifier circuit set forth in claim 2 wherein said digital circuit means further comprises reset circuit means for resetting said counter means prior to occurrence of said information portion in each of said envelope excursions whereby said analog signal can be maintained at said input circuit until said counter is reset.
Claim 6
Dependent Claim 65 words
The amplifier circuit as set forth in claim 4 wherein said digital circuit means further comprises gate means and oscillator means coupled to said counter means via said gate means, said gate means being enabled by said threshold out-put signal to repetitively increment said counter in response to a counting signal from said oscillator means so long as said output signal exceeds said predetermined level.
Claim 7
Dependent Claim 97 words
The amplifier circuit set forth in claim 2 wherein said information amplitude variations are pulse codes occurring during each envelope excursion with pulses in said codes having a predetermined amplitude relative to said peak envelope amplitude, and wherein said amplifier circuit further comprises a second threshold detector means to provide an incremental dead-band control signal when said output signal passes through a second predetermined level below said first-mentioned predetermined level, said incremental control signal being coupled to said input circuit along with said analog signal to suppress oscillation of said output signal about said second predetermined level.
Claim 8
Dependent Claim 216 words
An amplifier circuit comprising amplifier means having input means adapted to receive an input signal that comprises a series of generally square waves having amplitude variations therein representing predetermined information, said amplifier means having output means to develop an amplified version of said input signal and further having a predetermined gain such that peak amplitude of an uncompensated output signal would exceed a predetermined level, said amplifier circuit further comprising circuit means coupled between said output means and said input means to clamp peak amplitudes of said output signal at said predetermined level while maintaining said predetermined gain comprising threshold circuit means coupled to said output means to detect deviations in said outpuT signal above said predetermined level and provide a threshold output signal, counting circuit means enabled by said threshold output signal to provide a digital number signal representing said output deviation and digital-to-analog conversion means responsive to said digital number signal to provide an analog signal whose level varies according to said deviations above said predetermined level, said analog feedback signal being coupled to said amplifier input means so as to clamp said peak amplitudes of said out-put signal at said predetermined level while information variations in said output signal are substantially unchanged as compared to said information variations in said uncompensated output signal.
Claim 9
Dependent Claim 216 words
An amplifier circuit comprising amplifier means having input means adapted to receive an input signal that comprises a series of generally square waves having amplitude variations therein representing predetermined information, said amplifier means having output means to develop an amplified version of said input signal and further having a predetermined gain such that peak amplitude of an uncompensated output signal would exceed a predetermined level, said amplifier circuit further comprising circuit means coupled between said output means and said input means to clamp peak amplitudes of said output signal at said predetermined level while maintaining said predetermined gain comprising threshold circuit means coupled to said output means to detect deviations in said outpuT signal above said predetermined level and provide a threshold output signal, counting circuit means enabled by said threshold output signal to provide a digital number signal representing said output deviation and digital-to-analog conversion means responsive to said digital number signal to provide an analog signal whose level varies according to said deviations above said predetermined level, said analog feedback signal being coupled to said amplifier input means so as to clamp said peak amplitudes of said out-put signal at said predetermined level while information variations in said output signal are substantially unchanged as compared to said information variations in said uncompensated output signal.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-09-03 1977-03-05 1977-09-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-09-03 1981-03-05 1981-09-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-09-03 1985-03-05 1985-09-04 $7700.00 Window Closed / Lapsed

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