Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
136 words
A digital filter for providing an output signal when the frequency of a received cyclical signal exceeds either of specified upper and lower tolerances, comprising clock means for providing a timing pulse of known duration, a binary counter, gating means for coupling received signals to said counter during the occurrence of a timing pulse, first means responsive to the binary state of said counter to provide a first error signal until the counter reaches a specified minimum count, second means responsive to the binary state of said counter to provide a second error signal when the counter reaches a specified maximum count, means to provide an output signal in response to either of said error signals after the termination of a timing pulse, and means to clear said counter in the interval between successive timing pulses.
Claim 2
Dependent Claim
136 words
A digital filter for providing an output signal when the frequency of a received cyclical signal exceeds either of specified upper and lower tolerances, comprising clock means for providing a timing pulse of known duration, a binary counter, gating means for coupling received signals to said counter during the occurrence of a timing pulse, first means responsive to the binary state of said counter to provide a first error signal until the counter reaches a specified minimum count, second means responsive to the binary state of said counter to provide a second error signal when the counter reaches a specified maximum count, means to provide an output signal in response to either of said error signals after the termination of a timing pulse, and means to clear said counter in the interval between successive timing pulses.
Claim 3
Dependent Claim
31 words
The filter of claim 1 further including timing means for producing said timing pulses, said timing means providing a train of square wave pulses each having a duration of one second.
Claim 4
Dependent Claim
30 words
The filter of claim 2 wherein said means to clear said counter includes means in said timing means to produce a clear pulse in the interval between successive timing pulses.
Claim 5
Dependent Claim
24 words
The filter of claim 3 wherein said timing means further includes means to produce a sampling pulse at the termination of a timing pulse.
Claim 6
Dependent Claim
103 words
The filter of claim 4 wherein the means to produce said first and second error signals includes first and second NAND gates respectively, each of said gates being connected to receive signals from appropriate counter stages and wherein the means to provide an output signal includes a D-type flip-flop connected to receive error signals from each of said NAND gates as well as a sampling pulse from said timing means, said flip-flop being connected to remain in a first binary state until switched by an error signal, said flip-flop further being connected to produce an output signal when in said second binary state.
Claim 7
Dependent Claim
16 words
The filter of claim 5 wherein said second NAND gate is enabled by a sampling pulse.
Claim 8
Dependent Claim
81 words
The filter of claim 6 wherein the flip-flop contains P, D, CP and Q terminals, said first NAND gate being connected to said D terminal, said second NAND gate being coupled to said P terminal, said timing means being connected to provide sampling pulses to said CP terminal, said output signal being taken from said Q terminal, whereby said flip-flop is switched to the Q binary state in response to the simultaneous occurrence of a sampling pulse and an error signal.
Claim 9
Dependent Claim
77 words
The filter of claim 7 wherein the received signals are sine waves having a nominal frequency of 60 hertz, said filter further including limiting means for converting said sine waves into suitable logic level pulses, and wherein said counter includes at least seven stages, said first NAND gate being connected to receive signals from the stagEs representing 23, 24 and 25 counts, said second NAND gate being connected to receive signals from the stage representing 26 counts.