Time correcting device for electronic timepieces

Claim 2

An electronic timepiece comprising an oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider circuit means for sequentially dividing said high frequency time standard signal to produce a low frequency time keeping signal at each of a selected group of divider stages; display means including a plurality of display elements for the digital display of time; means for driving each of said display elements in response to the time deeping signal of one of said selected divider stages; and time correcting means including correction switch means coupled to each of the divider stages producing the 1 minute, 10 minute and 1 hour time keeping signal for selectively and individually applying a correction signal to each of said divider stages producing said 1 minute, 10 minute and 1 hour time keeping signals to correct the associated display elements, and reset switch means for separately and selectively applying a reset signal to the divider stages producing the 1 second and 10 second time keeping signals for returning to zero both of the display elements associated with said divider stages for producing said 1 second and 10 second time keeping signals.

Claim 3

An electronic timepiece as recited in claim 1, including means for interconnecting said correction switch means and an intermediate divider stage producing an intermediate frequency signal, said intermediate frequency signal serving as said correction signal.

Claim 4

An electronic timepiece comprising oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider circuit means for dividing said high frequency time standard signal and producing a time keeping signal at each of a plurality of said divider stages; display means for the digital display of time including a plurality of display elements; means for driving eaCh of said display elements in response to a time keeping signal produced by one of said divider stages; and time correcting means including a carry suppression gate between selected ones of the divider stages producing said time keeping signals; means for selectively applying a correction mode signal to said carry suppression gates, said carry suppression gates being adapted to permit the passage of signals between adjacent stages of said frequency divider circuit means in the absence of said correction mode signal but to prevent the transmission of signals between adjacent stages in the presence of said correction mode signal, and correction switch means for selectively applying a correction signal to each of a plurality of said divider stages producing said time keeping signals for selectively setting each of the display elements associated with the divider stages to which said switch means is connected, whereby a plurality of said display elements may be individually and independently corrected.

Claim 5

An electronic timepiece comprising oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider circuit means for dividing said high frequency time standard signal and producing a time keeping signal at each of a plurality of said divider stages; display means for the digital display of time including a plurality of display elements; means for driving eaCh of said display elements in response to a time keeping signal produced by one of said divider stages; and time correcting means including a carry suppression gate between selected ones of the divider stages producing said time keeping signals; means for selectively applying a correction mode signal to said carry suppression gates, said carry suppression gates being adapted to permit the passage of signals between adjacent stages of said frequency divider circuit means in the absence of said correction mode signal but to prevent the transmission of signals between adjacent stages in the presence of said correction mode signal, and correction switch means for selectively applying a correction signal to each of a plurality of said divider stages producing said time keeping signals for selectively setting each of the display elements associated with the divider stages to which said switch means is connected, whereby a plurality of said display elements may be individually and independently corrected.

Claim 6

An electronic timepiece as recited in claim 3, wherein said switch means includes means for separately applying said correction signal to each of the divider stages producing the 1 second, 10 second, 1 minute, 10 minute and 1 hour time keeping signals.

Claim 7

An electronic timepiece as recited in claim 4, including means for interconnecting said switch means and an intermediate divider stage for applying an intermediate freuency signal to said switch means for selective application to each of the divider stages to which said switch means is connected.

Claim 8

An electronic timepiece as recited in claim 5, wherein said interconnecting means includes a source of a D.C. correction signal, and a selection switch for selectively connecting said switch means to one of said intermediate divider stage for application of said intermediate frequency signal, an open circuit, to said source of D.C. correction signal whereby each of said divider stages connected to said switch means may be selectively corrected by either the one-time method or the quick-feed method.

Claim 9

An electronic timepiece comprising oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider means for dividing said high frequency time standard signal to produce a low frequency time keeping signal at each of said plurality of said divider stages; display means for the digital display of time including a display element for each digit of time to be displayed; means driving each of said display elements in response to a time keeping signal of one of said divider stages; and time correction means including switch means for selectively and individually applying a correction signal to each of a plurality of said divider stages for producing said time keeping signals, and means interconnecting said switch means and an intermediate divider stage producing an intermediate frequency signal, said intermediate frequency signal defining said correction signal.

Claim 10

An electronic timepiece comprising oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider means for dividing said high frequency time standard signal to produce a low frequency time keeping signal at each of said plurality of said divider stages; display means for the digital display of time including a display element for each digit of time to be displayed; means driving each of said display elements in response to a time keeping signal of one of said divider stages; and time correction means including switch means for selectively and individually applying a correction signal to each of a plurality of said divider stages for producing said time keeping signals, and means interconnecting said switch means and an intermediate divider stage producing an intermediate frequency signal, said intermediate frequency signal defining said correction signal.

Claim 11

An electronic timepiece as recited in claim 7, wherein said interconnecting means includes a source of a D.C. correction signal, and a selection switch for selectively connecting said switch means to one of said intermediate divider stages for application of said intermediate frequency signal, an open circuit, or said source of said D.C. correction signal whereby each of said divider stages connected to said switch means may be selectively corrected by either the one-time method or the quick-feed method.

Claim 12

An electronic timepiece as recited in claim 7, wherein at least one of the divider stages producing said time keeping signals includes a corresponding auxiliary divider circuit, said time correcting means including setting switch means for selectively applying a setting signal to each of said auxiliary divider circuits for permitting the setting of each of said auxiliary divider circuits to a selected value by the manual opening and closing of said setting switch means, and a gate mEans coupled to each divider stage having an auxiliary divider circuit and to said auxiliary divider circuit for detecting the respective states thereof and connected to receive the signal from the prior divider stage of said frequency divider circuit means, said intermediate frequency correction signal and a correction mode signal, said gate means being adapted to apply said intermediate frequency signal to said divider stage in response to said correction mode signal until said divider stage and associated auxiliary divider circuit are in the same state, and to thereafter prevent the application of said intermediate frequency signal and the signal from the prior stage to said divider stage, said gate means being further adapted to permit said divider stage to return to normal operation upon removal of said intermediate frequency signal and correction mode signal.

Claim 13

An electronic timepiece as recited in claim 9, wherein said gate means includes comparison gate means for producing an output signal when each divider stage and its associated auxiliary divider circuit are in the same state, a first AND gate means receiving the output signal of said comparison gate means and said correction mode signal; and a transmission gate means for transmitting the signal from the prior stage or said intermediate frequency correction signal to said divider stage in the absence of an output signal from said first AND gate means.