Data signal transmission system employing phase modulation

Claim 2

A data signal transmission system employing phase modulation wherein a carrier wave is phase-shifted once at every conversion point of at least one signal, comprising: means for receiving a data signal exhibiting two states representing first and second information states, driver means for generating at least one driving signal corresponding to said received data signal, said driving signal including at least two predetermined levels distributed symmetrically with respect to a predetermined reference level and transitions corresponding to the conversion points from one level to another in said data signal, said transitions occuring over a predetermined time interval equal to or greater than a time defined as phi max + phi min /W, but less than the period of the input data signal, phi max phi min, representing the maximum and minimum values of the phase shift angles of said carrier wave and W an angular frequency bandwidth, means for generating first and second carrier waves, one fixedly phase shifted substantiAlly 90* with respect to the other, first and second modulating means receiving said driving signal and said first and second carrier waves for generating a first and second modulated signals each of whose amplitudes is changed transitionally from one stable amplitude to another in response to said transitions and whose phase driving signal crosses said reference level, said stable amplitudes corresponding to said predetermined levels, and means for combining the modulated outputs from said first and second modulating means, thereby to provide said carrier phase shifted in response to the transistion of the data signals at each conversion point over said predetermined time interval, wherein amplitudes of said first and second modulated signals are changed so as to make the amplitude of the output of said combining means substantially constant, wherein a couple of said data signals are quaternary phase modulated, further comprising: a second driver means for generating second driving signals having at least two predetermined levels distributed symmetrically with respect to a second predetermined reference level and transition periods equal to said predetermined time interval, phase shifter means coupled to said combining means for fixedly shifting the output of said combining means by substantially 90*, third and fourth modulating means responsive to said second driving signals, and the output of said combining means and said phase shifter means for generating a third and fourth modulated signals each of whose amplitudes is changed transitionally from one further stable amplitude to another in response to said transitions and whose phase alternates by 180* when said second driving signals crosses said second reference level, said further stable amplitudes corresponding to said second predetermined levels, and second combining means for combining the modulated outputs from said third and fourth modulating means to deliver the quaternary phase modulated output signal in response to said data output signal.

Claim 3

The data signal transmission system of claim 1, wherein one of said data signals is binary phase modulated, and said driver means includes: first, second, third and fourth reference direct-current voltage sources whose voltages are +Vcc, -Vcc, +Vc, and -Vc respectively where Vcc and Vc are absolute values of said voltage sources and Vcc is greater than Vc, switching means for selectively connecting a center tap thereof to one of said first and second voltage sources in response to said first and second information states, a series circuit of two resistive elements, one end of said series circuit being connected to said center tap, a first diode element connected between said third voltage source and the intermediate junction of said series circuit, a second diode element connected between said fourth voltage source and said intermediate junction, a capacitor connected between another end of said series circuit and zero potential, and an output terminal connected to said another end for delivering said driving signal.

Claim 4

The data signal transmission system of claim 2, wherein said first modulating means includes; first and second amplifiers of input-balancing type, a variable impedance circuit coupled to the inputs of said first and second amplifiers for varying the input impedances to said first and second amplifiers in response to said data signal, and a summing circuit for summing the outputs of said amplifiers to deliver said first modulated signal.

Claim 5

The data signal transmission system of claim 3, wherein said second modulating means includes; a third amplifier, a variable impedance circuit coupled to the input of said third amplifier for varying the input impedance of said third amplifier in response to said data signal, and an output terminal pair coupled to sAid third amplifier for delivering said second modulated signal.

Claim 6

The data signal transmission system of claim 1, wherein said data signals are quaternary phase modulated, each of said first and second modulating means includes: first and second amplifiers of input-balancing type, a variable impedance circuit coupled to the inputs of said first and second amplifiers for varying the input impedances to said first and second amplifiers in response to said data signal, and a summing circuit for summing the outputs of said amplifiers to deliver each of said first and second modulated signals; and said driving circuit includes: a timing circuit for generating a clock pulse train and gating pulse trains whose pulse width corresponds to predetermined number of the clock pulses of said clock pulse train, a first logic circuit responsive to said data signals, said clock pulse train and said gating pulse trains for generating a burst clock pulse train with concentrated clock pulses in each period of said data signals, number of said concentrated clock pulses corresponding to the combination of levels of said data signals in each the period thereof, a second logic circuit responsive to said burst clock pulse train for generating first driving pulses, the leading and trailing edges of each of said first driving pulses corresponding to each successive couple of pulses among said concentrated clock pulses and being successively delayed by the clock period of said clock pulse train and for generating second driving pulses with leading and trailing edges corresponding to the last clock pulse in the preceding concentrated clock pulses and the first clock pulse in the succeeding concentrated clock pulses, wave form shaping circuits each having a couple of first reference voltage sources whose voltages are equal in absolute value to each other and greater than the maximum voltage among the voltages of said first reference direct current reference sources and opposite in polarity to each other, a plurality of second reference direct current voltage sources whose voltage correspond to upper-half of predetermined levels of said driving with respect to said predetermined reference level, a plurality of third reference direct current voltage sources whose voltages correspond to nether-half of said predetermined level, first switching means for selectively connecting a center tap thereof to one of said first voltage sources in response to a control signal, a series circuit of at least two diode elements connected unidirectionally, a second switching means for selectively connecting one end of said series circuit of diodes to one of said second reference voltage sources, a third switching means for selectively connecting another end of said series circuit of diodes to one of said third reference voltage sources, a control circuit receiving two driving signals each being selected from each of said first and second driving pulses for delivering said control signal to control said first switching means in response to which of said second or third reference voltage sources should be applied to said series circuit of diodes, a first resistor element connected between the center tap of said first switching means and the intermediate connecting point of said series circuit of diodes, a second resistor element whose one end is connected to said intermediate junction, a capacitor element connected between another end of said second resistor element and a substantial ground, and an output terminal connected to another end of said resistor element to deliver said driving signal.