Receiver decoder

Claim 2

A receiver operable from a signal having a first frequency carrier modulated at a second frequency and also containing a third frequency at a frequency lower than said carrier frequency, said receiver comprising in combination, first means responsive to said first frequency, a main load, second means responsive to said second frequency connected to receive an input from said first responsive means and connected to supply an output to said main load in the presence of a received signal containing said first and second frequencies, disabling means connected to one of said responsive means and operative in the absence of a received signal containing said third frequency to disable output to said main load, and third means responsive to said third frequency and having an output connected to terminate said disabling means output for at least a time period to enable output to said main load upon the presence of a received signal containing said second frequency in addition to said first and third frequencies.

Claim 3

A receiver as set forth in claim 1, wherein said first responsive means is means tuned to resoNance at said first frequency.

Claim 4

A receiver as set forth in claim 1, wherein said second responsive means includes means tuned to resonance at said second frequency.

Claim 5

A receiver as set forth in claim 1, wherein said third responsive means is means tuned to resonance at said third frequency.

Claim 6

A receiver as set forth in claim 1, wherein said disabling means includes means establishing a DC bias voltage of a given value.

Claim 7

A receiver as set forth in claim 1, including means responsive primarily to noise and off-frequency signals developing a voltage connected in opposition to the output of said second responsive means.

Claim 8

A receiver as set forth in claim 6, wherein said main load includes semi-conductor means having a forward conducting threshold value, and means connecting the outputs of said noise responsive means and said second responsive means in opposition to apply to said semi-conductor means a voltage less than said threshold value in the absence of a received signal containing said second and third signals.

Claim 9

A receiver operable from a signal having a first frequency carrier modulated at a second frequency and also containing a third frequency at a frequency lower than said carrier frequency, said receiver comprising in combination, a detector circuit having first and second terminals, means connected to pass to said detector circuit signals lower than said first frequency, a main load, means connected to pass current from one of said terminals to said main load upon the voltage from said first to said second terminal becoming more positive than a given value, first means in said detector circuit responsive to said second frequency therein and having an output connected to said terminals which output from said first to said second terminal is more positive than said given value in the presence of a received signal containing said second frequency, bias means in said detector circuit having an output connected to said terminals which bias output from said first to said second terminal is more negative than said given value in the absence of a received signal containing said third frequency, and second means in said detector circuit responsive to said third frequency therein and having an output connected to terminate said bias means output for at least a time period to enable said detector circuit by establishing the voltage from said first to said second terminal more positive than said given value to thus pass current to said main load upon the presence of a received signal containing said second frequency in addition to said first and third frequencies.

Claim 10

A receiver operable from a signal having a first frequency carrier modulated at a second frequency and also containing a third frequency at a frequency lower than said carrier frequency, said receiver comprising in combination, a detector circuit having first and second terminals, means connected to pass to said detector circuit signals lower than said first frequency, a main load, means connected to pass current from one of said terminals to said main load upon the voltage from said first to said second terminal becoming more positive than a given value, first means in said detector circuit responsive to said second frequency therein and having an output connected to said terminals which output from said first to said second terminal is more positive than said given value in the presence of a received signal containing said second frequency, bias means in said detector circuit having an output connected to said terminals which bias output from said first to said second terminal is more negative than said given value in the absence of a received signal containing said third frequency, and second means in said detector circuit responsive to said third frequency therein and having an output connected to terminate said bias means output for at least a time period to enable said detector circuit by establishing the voltage from said first to said second terminal more positive than said given value to thus pass current to said main load upon the presence of a received signal containing said second frequency in addition to said first and third frequencies.

Claim 11

A receiver as set forth in claim 8, wherein said first responsive means includes a circuit tuned to resonance at said second frequency.

Claim 12

A receiver as set forth in claim 8, wherein said second responsive means includes means tuned to resonance at said third frequency.

Claim 13

A receiver as set forth in claim 8, wherein said receiver is a remote control receiver operable from a signal of a transmitter transmitting a first frequency carrier modulated at said second frequency and interrupted at said third frequency which is lower than said second frequency.

Claim 14

A receiver as set forth in claim 8, wherein said main load includes a relay, a transistor connected to energize and relay and a diode poled said conduct current from said first terminal through input electrodes of said transistor to said second terminal upon the voltage between said first and second terminals exceeding said given value which is determined by the forward voltage drops of said diode and said transistor input electrodes.

Claim 15

A receiver as set forth in claim 8, wherein said second responsive means includes removable connections to said first and second terminals of said detector circuit to permit the receiver to be operable with the second responsive means removed and operable on a signal having said first frequency carrier modulated at said second frequencY.

Claim 16

A receiver as set forth in claim 8, including a test point jack connected to said first and second terminals, and a test plug connected to the input of said second responsive means and removably connectable with said test point jack.

Claim 17

A receiver as set forth in claim 8, wherein said bias means includes a transistor, power supply means connecting said transistor to conduct current from said second to said first terminal, and said second responsive means including means to terminate conduction of said transistor to terminate said bias means output.

Claim 18

A receiver as set forth in claim 8, including means to establish said third frequency on said first terminal and also said bias output of said bias means on said first terminal.

Claim 19

A receiver as set forth in claim 8, including means in said detector circuit responsive primarily to noise and off-frequency signals and having an output connected to said terminals which output from said first to said second terminal is more negative than said given value in the absence of a received signal containing said second frequency.

Claim 20

A receiver as set forth in claim 17, wherein said first responsive means output is connected in opposition to the output of said noise responsive means.

Claim 21

A receiver as set forth in claim 8, wherein said third frequency responsive means includes a parallel resonant circuit.

Claim 22

A receiver as set forth in claim 8, wherein said third frequency responsive means includes a tuning fork.

Claim 23

A receiver decoder, comprising, in combination, a first terminal, bias means to develop a bias voltage, switch means connected to said bias means to selectively connect and disconnect said bias voltage from said first terminal, frequency responsive means having an output and having an input connected to be responsive to a given frequency input on said first terminal, and means connecting the output of said frequency responsive means to said switch means to actuate said switch means and change the bias voltage condition on said first terminal upon the presence of said given frequency.

Claim 24

A receiver decoder, comprising, in combination, a first terminal, bias means to develop a bias voltage, switch means connected to said bias means to selectively connect and disconnect said bias voltage from said first terminal, frequency responsive means having an output and having an input connected to be responsive to a given frequency input on said first terminal, and means connecting the output of said frequency responsive means to said switch means to actuate said switch means and change the bias voltage condition on said first terminal upon the presence of said given frequency.

Claim 25

A receiver decoder as set forth in claim 21, including power supply means, and means connecting said bias means to said power supply means to develop said bias voltage.

Claim 26

A receiver decoder as set forth in cliam 21, wherein said bias voltage is a DC voltage.

Claim 27

A receiver decoder as set forth in cliam 21, wherein said bias voltage is a DC voltage.

Claim 28

A receiver decoder as set forth in claim 21, including a second terminal, and means connecting said frequency responsive means input to said first and second terminals to be responsive to a given frequency signal therebetween.

Claim 29

A receiver decoder as set forth in claim 21, including a second terminal, and means connecting said switch means to said bias means to selectively connect and disconnect said bias voltage between said first and second terminals.

Claim 30

A receiver decoder as set forth in claim 21, including second and third terminals adapted to have an AC voltage applied thereacross, and power supply means including a rectifier connected to said second and third terminals to develop a DC bias voltage.

Claim 31

A receiver decoder as set forth in claim 21, wherein said means connecting the output of said frequency responsive means actuates said switch means to disconnect said bias voltage from said first terminal upon the presence of said given frequency.

Claim 32

A receiver decoder as set forth in claim 21, wherein said switch means includes a transistor biased into a conducting condition for the switch closed condition and biased into a non-conducting condition for the switch open condition.

Claim 33

A receiver decoder as set forth in claim 21, including second and third terminals adapted to have an AC voltage applied thereacross, and means connecting said bias means to said second and third terminals to develop a bias voltage between said first and second terminals.

Claim 34

A receiver decoder as set forth in claim 29, including power supply means, sAid power supply means including rectifier and filter means connected to said second and third terminals to develop a DC bias voltage between said first and second terminals.

Claim 35

A receiver decoder as set forth in claim 21, including timing means, and means to activate said timing means for a time delay of applying said bias voltage to said first terminal upon cessation of said given frequency input on said first terminal.

Claim 36

A receiver decoder as set forth in claim 21, including a time delay capacitor, means to charge said capacitor for a time delay of applying said bias voltage to said first terminal.

Claim 37

A receiver decoder as set forth in claim 21, wherein said frequency responsive means includes a parallel resonant circuit.

Claim 38

A receiver decoder as set forth in claim 21, wherein said frequency responsive means includes a mechanically vibratable tuning fork.