US3753238A
Expired / Lapsed
US
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Distributed logic memory cell with source and result buses
Assignee: AT&T Inc
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Filing: 1971-08-27
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Granted: 1973-08-14
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Expires: 1991-08-27
Abstract
Abstract A distributed logic memory cell for a parallel cellular logic processor has a selectable-logic-operation circuit for coupling signals from a single-conductor source bus to a single-conductor result bus. Equally ranked control flip-flop circuits are also selectable for coupling signals in the opposite direction between the buses, as well as coooperating with instruction signals from a central control to determine whether or not a particular cell will be allowed to respond to other signals applied from the central control unit to all cells of the processor. Control signals are provided on a binary coded basis and decoded within each cell.
Inventors
- 👤 D Tutelman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/1733; H03K19/17736
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
179 words
A parallel cellular logic system including at least one distributed logic memory cell, each said distributed logic memory cell comprising means for performing different selectable types of logic operations, said performing means including a data signal input connection for receiving signals upon which operations are to be performed and a control signal input connection for receiving control signals to determine a type of said logic operations, a source bus coupled for supplying data signals to said data signal input connection of said performing means, a result bus coupled to receive a result signal from said logic operation circuit for distribution of said result signal to a selectable circuit destination within said cell, plural selectively actuatable control bistable circuits connected for coupling result signals to said source bus from said result bus, means, responsive to predetermined combinations of output signals of said control bistable circuits, for producing a cell enabling signal, controllable means for selecting for actuation, and thus as said circuit destination, one of said bistable circuits, and means for coupling said enabling signal to enable said selecting means.
Claim 2
Dependent Claim
179 words
A parallel cellular logic system including at least one distributed logic memory cell, each said distributed logic memory cell comprising means for performing different selectable types of logic operations, said performing means including a data signal input connection for receiving signals upon which operations are to be performed and a control signal input connection for receiving control signals to determine a type of said logic operations, a source bus coupled for supplying data signals to said data signal input connection of said performing means, a result bus coupled to receive a result signal from said logic operation circuit for distribution of said result signal to a selectable circuit destination within said cell, plural selectively actuatable control bistable circuits connected for coupling result signals to said source bus from said result bus, means, responsive to predetermined combinations of output signals of said control bistable circuits, for producing a cell enabling signal, controllable means for selecting for actuation, and thus as said circuit destination, one of said bistable circuits, and means for coupling said enabling signal to enable said selecting means.
Claim 3
Dependent Claim
58 words
The system in accordance with claim 1 in which each distributed logic memory cell comprises in addition an additional bistable circuit coupled to provide signals to another data signal input of said performing means, and means for coupling result signals from said result bus to an input of said additional bistable circuit to control the stable state thereof.
Claim 4
Dependent Claim
23 words
The system in accordance with claim 1 in which said source and result buses each consists of a single conductor within a cell.
Claim 5
Dependent Claim
65 words
The system in accordance with claim 1 in which each distributed logic memory cell comprises in addition multibit data store means, means for selectively addressing individual bit locations of said store means, means for storing result signals from said result bus in an addressed location of said data store means, and means for coupling an output of said data store means to said source bus.
Claim 6
Dependent Claim
56 words
The system in accordance with claim 1 which comprises in addition external data signal circuit means, means in each of said cells for selectively coupling external data signals from said circuit means to said source bus, and means in each of said cells for selectively coupling to said circuit means result signals from said result bus.
Claim 7
Dependent Claim
61 words
The system in accordance with claim 1 in which said system comprises in addition a read bus, and each distributed logic memory cell comprises in addition means for coupling an output of said performing means to said read bus, and means for coupling said enabling signal produced in such distributed logic memory cell to actuate the performing means output coupling means.
Claim 8
Dependent Claim
142 words
The system in accordance with claim 1 which includes a plurality of said distributed logic memory cells and comprises in addition means for interconnecting said distributed logic memory cells in a predetermined ordered sequence for global communication among such cells, said interconnecting means including in each of said distributed logic memory cells a first pair of intercell coupling gates connected in said interconnecting means for coupling signals from a source bus of an adjacent cell on one side in said sequence to said source bus and said result bus, respectively, of the cell containing such gates, and a second pair of intercell coupling gates connected in said interconnecting means for coupling signals from a source bus of an adjacent cell on the other side in said sequence to said source bus and said result bus, respectively, of the cell containing such gates.
Claim 9
Dependent Claim
56 words
The system in accordance with claim 7 in which there are provided in each of said distributed logic memory cells means for connecting an output of one of said control bistable circuits to disable the one gate in each of said pairs of gates of the same cell which otherwise provides connection between cell source buses.
Claim 10
Dependent Claim
97 words
The system in accordance with claim 1 which includes a plurality of said distributed logic memory cells and in which system a control unit is provided for supplying plural sets of signals, each set defining on a binary coded basis a particular circuit selection in common for all of said distributed logic memory cells, and each of said distributed logic memory cells includes means for coupling one of said sets to said controllable selecting means, the last-mentioned selecting means including means for decoding said one set of signals to control said destination, and thus said actuation, selection.
Claim 11
Dependent Claim
75 words
The system in accordance with claim 9 in which said result bus in each cell is a single conductor bus for transmitting said output data signals in single-rail logic format, and said selecting means in each cell includes means for converting single-rail logic signals on said result bus into double-rail logic signals, with complementary signal waveforms on each of two signal paths at inputs of each of said bistable circuits, For controlling said bistable circuits.
Claim 12
Dependent Claim
71 words
The system in accordance with claim 9 in which in each distributed logic memory cell said performing means includes a further data signal input connection, a further bistable circuit is provided for selectively coupling signals to said further input connection in response to signals on said result bus, and means are provided to couple another binary coded signal set from said control unit directly to said control input connections without decoding.
Claim 13
Dependent Claim
96 words
The system in accordance with claim 1 in which in each distributed logic memory cell each of said control bistable circuits has a first and a second output connection at which complementary output signal waveforms are produced, means are provided for coupling said first output connection of each control bistable circuit to said source bus to provide the aforesaid result signal coupling thereto, and said enabling signal producing means includes means for coupling said second output connection of each control bistable circuit to said enabling signal producing means for providing said predetermined combinations of output signals.
Claim 14
Dependent Claim
123 words
The system in accordance with claim 12 in which in each distributed logic memory cell said result bus is a single conductor bus for transmitting said output data signals in single-rail logic format, said selecting means includes means for converting result bus signals to a double-rail logic format, wherein complementary signal wave formats appear on each of two signal paths at inputs of each of said bistable circuits, said converting means comprising for each of said bistable circuits means for applying said single-rail logic signals from said result bus to a first input connection of such bistable circuit, and inverting gate means for coupling signals at said first input connection of such bistable circuit to a second input connection of such bistable circuit.
Claim 15
Dependent Claim
98 words
The system in accordance with claim 1 in which said enabling signal producing means comprises a plurality of coincidence gates, means for connecting like outputs of said gates together to said enabling signal coupling means, and means for selectively enabling said gates for actuation, and said means for coupling control bistable circuit outputs to said enabling signal producing means includes means connecting to an input of each gate an output of a different one of said bistable circuits, which output has signals that are the complement of signals provided by the same bistable circuit to said source bus.
Claim 16
Dependent Claim
173 words
In combination, a plurality of bistable switching devices each having input means for controlling the operation thereof, a plurality of signal sources, said sources including outputs of at least a portion of said devices means for supplying in multiple data signals to input means of all of said devices from a selectable one of said sources, said supplying means including means for combining a signal from said one source with an additional signal in accordance with at least one predetermined logical function, means, in said input means, for selectively enabling at least one of said devices for actuation to a state representative of said data signals, a plurality of circuits for providing different condition control signal combinations, each of said control signal combinations corresponding to a different one of said devices in said portion of devices, means, responsive to coincidence of any one of said condition control signal combinations and a predetermined stable state of the corresponding one of said switching devices, respectively, for supplying a signal for disabling said device input means.
Claim 17
Dependent Claim
173 words
In combination, a plurality of bistable switching devices each having input means for controlling the operation thereof, a plurality of signal sources, said sources including outputs of at least a portion of said devices means for supplying in multiple data signals to input means of all of said devices from a selectable one of said sources, said supplying means including means for combining a signal from said one source with an additional signal in accordance with at least one predetermined logical function, means, in said input means, for selectively enabling at least one of said devices for actuation to a state representative of said data signals, a plurality of circuits for providing different condition control signal combinations, each of said control signal combinations corresponding to a different one of said devices in said portion of devices, means, responsive to coincidence of any one of said condition control signal combinations and a predetermined stable state of the corresponding one of said switching devices, respectively, for supplying a signal for disabling said device input means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |