Bandpass filter using plural commutating capacitor units

Claim 2

In combination, a bandpass filter comprising a plurality of commutating capacitor units connected in a like plurality of shunt branches of said filter, each of said units including a plurality of interconnected capacitors and means for commutating said interconnected capacitors between input and output connections of such unit, and means for driving said commutating means for each of said units in different phases with respect to one another for substantially equalizing responses of said filter at cutoff frequencies thereof.

Claim 3

The combination in accordance with claim 1 in which, two of said units are provided, and said driving means comprises means for driving said units at approximately a 30* phase difference with respect to one another as measured on a wave of the frequency of commutation of one of said units.

Claim 4

The combination in accordance with claim 1 in wHich, two of said units are provided, and each of said units includes at least three interconnected capacitors all of approximately the same capacitance.

Claim 5

The combination in accordance with claim 1 in which said filter comprises, a 3-element, pi -section, bandpass filter having an impedance connected in series in a through signal path of said filter between connection points for successive ones of said plurality of shunt branches.

Claim 6

The combination in accordance with claim 1 in which each of said units comprises, an input connection and an output connection, a plurality of capacitors interconnected with one another in a circuit having a predetermined number, greater than two, of terminals, and means for coupling the terminals of different paired combinations of said terminals to said input and output connections, respectively, in a predetermined recurring sequence of time intervals, each of said combinations including in series therebetween at least two of said capacitors.

Claim 7

A signal frequency sensitive circuit comprising a plurality of interconnected commutatable capacitor units, each of said units including a plurality of interconnected capacitors, and means for commutating different combinations of said interconnected capacitors through a predetermined sequence of connection combinations between input and output connections of such unit, each of said combinations including at least two capacitors, and means for driving said commutating means for each of said interconnected units in different phase with respect to one another.

Claim 8

A signal frequency sensitive circuit comprising a plurality of interconnected commutatable capacitor units, each of said units including a plurality of interconnected capacitors, and means for commutating different combinations of said interconnected capacitors through a predetermined sequence of connection combinations between input and output connections of such unit, each of said combinations including at least two capacitors, and means for driving said commutating means for each of said interconnected units in different phase with respect to one another.

Claim 9

The frequency sensitive circuit in accordance with claim 6 in which, each of said combinations includes means for connecting said two capacitors in series between the input and output terminals of the unit including such capacitors, and each of the two capacitors is also included in a different one of said combinations, respectively.

Claim 10

A signal frequency sensitive circuit comprising a plurality of interconnected commutatable capacitor units, each of said units including a plurality of interconnected capacitors and means for commutating said interconnected capacitors through a predetermined sequence of connection combinations between input and output connections of such unit, said sequence of combinations including the connection of each combination once with each polarity between said input and output connections, and means for driving said commutating means for each of said interconnected units in different phases with respect to one another.

Claim 11

A signal frequency sensitive circuit comprising a plurality of interconnected commutatable capacitor units, each of said units including a plurality of interconnected capacitors and means for commutating said interconnected capacitors through a predetermined sequence of connection combinations between input and output connections of such unit, said sequence of combinations including the connection of each combination once with each polarity between said input and output connections, and means for driving said commutating means for each of said interconnected units in different phases with respect to one another.