Digital frequency comparator

Claim 2

A circuit for detecting changes in the frequency of a signal which comprises: means for generating first pulse signals representative of the occurrence of the rise and fall times of an applied pulse signal; means having stable and unstable modes of operation for generating second pulse signals in response to each of said first pulse signals, the normal time interval of said unstable mode being representative of a predetermined reference frequency, said unstable time interval being reinitiated in reSponse to each of said first pulse signals; means responsive to said first and second pulse signals for generating third pulse signals representative of intervals when individual ones of said first pulse signals occur during intervals of said second pulse signals; and means selectively responsive to said second and third pulse signals for generating a fourth pulse signal representative of intervals when the frequency of said applied signal is greater than and less than said reference frequency.

Claim 3

The invention as defined in claim 1 wherein said third pulse signal generating means includes logic network means being responsive to the momentary simultaneous application of said first and second pulse signals to generate said third pulse signals.

Claim 4

The invention as defined in claim 2 wherein said second pulse signal generating means includes a retriggerable monostable multivibrator having a predetermined timing interval, said multivibrator being responsive to each of said first pulse signals for initiating substantially instantaneously generation of a corresponding one of said timing intervals.

Claim 5

The invention as defined in claim 3 wherein said logic network means includes a coincidence gate.

Claim 6

The invention as defined in claim 4 wherein said fourth pulse signal generating means includes bistable switching means selectively responsive to said second and third pulse signals for generating said fourth pulse signal.

Claim 7

A digital frequency comparator which comprises: means for generating first pulse signals representative of the occurrence of each change of state of an applied signal; means responsive to said first pulse signals for generating second pulse signals normally having a predetermined interval representative of a reference frequency, said predetermined interval being reinitiated in response to each one of said first pulse signals; means responsive to said first and second pulse signals for generating third pulse signals representative of intervals when said first and second pulse signals are concurrently in a predetermined state, said concurrence occurring only when individual ones of said first pulse signals occur during the interval of said second pulse signals; and means selectively responsive to said second and third pulse signals for generating a fourth pulse signal representative of intervals when the frequency of said applied signal is greater than and less than said reference frequency.

Claim 8

A digital frequency comparator which comprises: means for generating first pulse signals representative of the occurrence of each change of state of an applied signal; means responsive to said first pulse signals for generating second pulse signals normally having a predetermined interval representative of a reference frequency, said predetermined interval being reinitiated in response to each one of said first pulse signals; means responsive to said first and second pulse signals for generating third pulse signals representative of intervals when said first and second pulse signals are concurrently in a predetermined state, said concurrence occurring only when individual ones of said first pulse signals occur during the interval of said second pulse signals; and means selectively responsive to said second and third pulse signals for generating a fourth pulse signal representative of intervals when the frequency of said applied signal is greater than and less than said reference frequency.

Claim 9

The invention as defined in claim 6 wherein said second pulse signal generating means includes a retriggerable monostable multivibrator having a predetermined timing interval.

Claim 10

The invention as defined in claim 7 wherein said third pulse signal generating means includes coincidence gate means.

Claim 11

The invention as defined in claim 8 wherein said coincidence gate means includes a NAND gate having first and second inputs and an output, said first pulse signals being supplied to said first input and said second pulse signals being supplied to said second input and said third pulse signals being developed at said output.

Claim 12

The invention as defined in claim 9 wherein said fourth pulse signal generating means includes bistable switching means having a set input, a reset input and an output, said second pulse signals being supplied to said reset input, said third pulse signals being supplied to said set input and said bistable switching means being selectively responsive to said second and third pulse signals for generating said fourth pulse signal at said output, wherin predetermined states of said fourth pulse signal represent intervals when the frequency of said applied signal is greater than and less than said reference frequency.