Circuit for reducing pulse pile-up in pulse detection systems

Claim 2

In a radioactivity well logging system having a pulsed neutron source and a radioactivity detector wherein electrical pulses tend to pile up within the system, the improvement comprising means to selectively gate and transmit to the earth''s surface a first electrical pulse indicative of detected radiation following the commencement of each neutron source pulse and to gate a second such electrical pulse and to transmit said second electrical pulse to the earth''s surface only after a predetermined delay following the transmission of said first electrical pulse.

Claim 3

In the system according to claim 1, said selective gating means being further characterized as being synchronized with the pulsing of said neutron source.

Claim 4

In the system according to claim 2, said selective gating means being further characterized as including means to discriminately gate only those pulses having a predetermined characteristic.

Claim 5

In the system according to claim 3, wherein said predetermined characteristic is functionally related to the energy level of gamma rays of interest emanating from the formations surrounding the well bore.

Claim 6

In a radioactivity well logging system having a pulsed neutron source and a radioactivity detector wherein electrical pulses tend to pile up within the system, the improvement comprising means to selectively gate a plurality of electrical pulses indicative of detected radiation following the commencement of each neutron source pulse, said means including delay means for introducing predetermined delays between said electrical pulses prior to their transmission to the earth''s surface.

Claim 7

In a radioactivity well logging system having a pulsed neutron source and a radioactivity detector wherein electrical pulses tend to pile up within the system, the improvement comprising means to selectively gate a plurality of electrical pulses indicative of detected radiation following the commencement of each neutron source pulse, said means including delay means for introducing predetermined delays between said electrical pulses prior to their transmission to the earth''s surface.

Claim 8

In the system according to claim 5, said selective gating means being further characterized as being synchronized with the pulsing of said neutron source.

Claim 9

In the system according to claim 6, said selective gating means being further characterized as including means to discriminately gate only those pulses having a predetermined characteristic.

Claim 10

In the system according to claim 7, wherein said predetermined characteristic is functionally related to the energy level of gamma rays of interest emanating from the formations surrounding the well bore.

Claim 11

In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical AND gate having one of its three inputs connected to said input terminal; a J-K flip-flop circuit having a first input steering terminal, a clearing input terminal and a clock input terminal and providing an output signal at an output terminal of said flip-flop circuit, said clearing input terminal being connected to said clock means and also to the second input of said first AND gate and said input steering terminal of said J-K flip-flop circuit being connected to the output terminal of said flip-flop circuit and to the third input of said first AND gate; a plurality of additional AND gates having two Inputs each; a single shot multivibrator connected to, and driven by, the output of said first AND gate, the output of said multivibrator being connected to the first input of each of said additional gates for triggering said gates; a scaler-decoder connected to the output of said multivibrator, the outputs of said decoder being connected to the second inputs of said additional gates, respectively, the last used decoder output being connected to said clock input terminal of said J-K flip-flop circuit; a plurality of linear gates, each of which is connected to the output of said delay means, and such linear gates being connected to be triggered by the outputs of the plurality of additional AND gates, respectively; and an output terminal connected to the outputs of said linear gates.

Claim 12

In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical AND gate having one of its three inputs connected to said input terminal; a J-K flip-flop circuit having a first input steering terminal, a clearing input terminal and a clock input terminal and providing an output signal at an output terminal of said flip-flop circuit, said clearing input terminal being connected to said clock means and also to the second input of said first AND gate and said input steering terminal of said J-K flip-flop circuit being connected to the output terminal of said flip-flop circuit and to the third input of said first AND gate; a plurality of additional AND gates having two Inputs each; a single shot multivibrator connected to, and driven by, the output of said first AND gate, the output of said multivibrator being connected to the first input of each of said additional gates for triggering said gates; a scaler-decoder connected to the output of said multivibrator, the outputs of said decoder being connected to the second inputs of said additional gates, respectively, the last used decoder output being connected to said clock input terminal of said J-K flip-flop circuit; a plurality of linear gates, each of which is connected to the output of said delay means, and such linear gates being connected to be triggered by the outputs of the plurality of additional AND gates, respectively; and an output terminal connected to the outputs of said linear gates.

Claim 13

The circuit according to claim 9, including in addition thereto, a reset generator for resetting said scaler-decoder in synchronization with said clock pulses.

Claim 14

The circuit according to claim 10, including in addition thereto, additional delay means connected to the outputs of at least one of said linear gates.

Claim 15

In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical AND gate having one of its three inputs connected to said input terminal; a J-K flip-flop circuit having a first input steering terminal, a clearing input terminal and a clock input terminal and providing an output signal at an output terminal of said flip-flop circuit, said clearing input terminal being connected to said clock means and also to the second input of said first AND gate and said input steering terminal of said J-K flip-flop circuit being connected to the output terminal of said flip-flop circuit and to the third input of said first AND gate; a plurality of additional AND gates having two inputs each; a single shot multivibrator connected to, and driven by, the output of said first AND gate, the output of said multivibrator being connected to the first input of each of said additional gates for triggering said gates; a scaler-decoder connected to the output of said multivibrator, the outputs of said decoder being connected to the second inputs of said additional gates, respectively, the last used decoder output being connected to said clock input terminal of said J-K flip-flop circuit; a plurality of charge and hold circuits, each of which is connected to the output of said delay means, and such charge and hold circuits being connected to be triggered by the outputs of the plurality of additional AND gates, respectively; means to interrogate said charge and hold circuits; and an output terminal connected to said interrogator means.

Claim 16

In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical AND gate having one of its three inputs connected to said input terminal; a J-K flip-flop circuit having a first input steering terminal, a clearing input terminal and a clock input terminal and providing an output signal at an output terminal of said flip-flop circuit, said clearing input terminal being connected to said clock means and also to the second input of said first AND gate and said input steering terminal of said J-K flip-flop circuit being connected to the output terminal of said flip-flop circuit and to the third input of said first AND gate; a plurality of additional AND gates having two inputs each; a single shot multivibrator connected to, and driven by, the output of said first AND gate, the output of said multivibrator being connected to the first input of each of said additional gates for triggering said gates; a scaler-decoder connected to the output of said multivibrator, the outputs of said decoder being connected to the second inputs of said additional gates, respectively, the last used decoder output being connected to said clock input terminal of said J-K flip-flop circuit; a plurality of charge and hold circuits, each of which is connected to the output of said delay means, and such charge and hold circuits being connected to be triggered by the outputs of the plurality of additional AND gates, respectively; means to interrogate said charge and hold circuits; and an output terminal connected to said interrogator means.

Claim 17

The circuit according to claim 12 wherein said interrogator means includes a separate interrogator circuit for each of said plurality of charge and hold circuits.

Claim 18

The circuit according to claim 13, including in addition thereto, means to gate said separate interrogator circuits connected to the outputs of said additional AND gates.

Claim 19

The circuit according to claim 14, including in addition thereto, discriminator means between said input terminal and said first AND gate.