Solid state video reproducing system

Claim 2

An electronic solid state video reproducing system for displaying a video input signal comprising timing pulse means, first circuit means responsive to said timing pulse means, a plurality of video storage elements respectively including a like plurality of signal driver means and a like plurality of associated signal storage means responsive to said first circuit means and the video input signal for storing the video input signal, said plurality of said signal driver means respectively including a like plurality of luminescence means to provide with each of said signal storage menas an associated one of said luminescence means, and triggering means for causing said plurality of signal driver means to read out simultaneously the video input signal stored in said plurality of signal storage means causing said plurality of liminescence means to luminesce simultaneously and provide a complete video image.

Claim 3

The system of claim 1 in which is included a substrate and said plurality of signal driver means additionally includes anode means common to each of said plurality of signal driver means, said substrate having deposited thereon: said plurAlity of signal driver means including said anode means and said plurality of liminescence means, said timing pulse means, said first circuit means, said plurality of signal storage means, and said triggering means; and in which said triggering means includes means for applying a luminescence pulse to said anode means for causing said plurality of signal driver means to read out the video input signal stored in said plurality of signal storage means.

Claim 4

The system of claim 2 in which said timing pulse means includes means for generating a field termination pulse and said luminescence pulse generator means being gated into operation by said field termination pulse.

Claim 5

The system of claim 2 in which said plurality of luminescence means respectively include a plurality of microscopic isolated particles which luminesce when a voltage is applied thereacross and said plurality of signal driver meu0s respectively include a plurality of transistors.

Claim 6

The system of claim 4 in which said p urality of transistors respectively include drains, said luminescence particles respectively being bonded to said drains, and said anode means comprises a plurality of microscopic particles of a transparent conductive material respectively being bonded to said luminescence particles and being interconnected one with the other establishing said anode means.

Claim 7

The system of claim 4 in which said plurality of signal driver means respectively include a plurality of diodes respectively having anodes, said luminescence particles respectively being bonded to said anodes, and said anode means cimprises a plurality of microscopic particles of a transparent conductive material respectively being bonded to said luminescence particles and being interconnected and with the other establishing said anode means.

Claim 8

The system of claim 4 in which said particles of electro-luminescent material consist of a substance for causing said video image to be provided in black and white.

Claim 9

The system of claim 4 in which said particles of electro-luminescent particles consist of color triads for causing said video image to be provided in a multi-colored natural-like image.

Claim 10

The system of claim 4 in which said electro-luminescent particles are uniformly arranged on said substrate in row and column configuration.

Claim 11

The system of claim 9 in which said first circuit means responsive to said timing pulse means comprises row logic means; a plurality of line gate pulse generating means, a plurality of video line gate means, and column logic means; and in which said plurality of signal storage means respectively comprise a plurality of second circuit means and an equal number of associated storage capacitors, said first circuit means selectively and sequentially controlling the application of a variety of certain voltages across said plurality of electro-luminescent particles, said row logic means includes means for generating at least a first pulse for each of said rows of electroluminescent particles said line gate pulse generator means respectively being coupled to said video line gate means and said column logic means and responsive to said first pulse to generate a second pulse of predetermined duration to trigger said column logic means, said column logic means includes means responsive to said line gate pulse generating means for generating a third pulse for each of said columns, said video line gate means being responsive to said second pulse and the video input signal to provide a plurality of discrete bits of the video input signal to said plurality of second circuit means, said second circuit means being individually responsive to one of said plurality of third pulses and to one of said plurality of discrete bits of the video input signal to permit the output thereof to charge an associated one of said plurality of storage capacitors in proportion to the amplitude of one of said plurality of discrete bits of the video input signal.

Claim 12

The system of claim 10 in Which said row and column logic means respectively consists of ring counter circuits.

Claim 13

The system of claim 10 in which said means for generating said second pulse consists of a monostable multivibrator circuit.

Claim 14

The system of claim 10 in which said timing pulse means includes means for generating a frame termination pulse and in which said means for generating said luminescence pulse comprises storage capacitor means and silicon controlled rectifier means being gated into operation by said frame termination pulse.

Claim 15

The system of claim 10 in which said first circuit means comprises a plurality of line gate pulse generating means; a plurality of video line gate means, column logic means, first and second row logic means and electronic switching means for alternately gating said first and second row logic means; said first row logic means includes means for generating a fourth pulse for each even numbered ones of said plurality of line gate pulse generating means, said second row logic means includes means for generating a fifth pulse for each odd numbered ones of said plurality of line gate pulse generating means; even numbered ones of said line gate pulse generator means being respectively coupled to even numbered ones of said video line gate means, coupled to said column logic means, and being responsive to said fourth pulse to generate said second pulse; odd numbered ones of said line gate pulse generator means being respectively coupled to odd numbered ones of said video line gate means, coupled to said column logic means, and being responsiVe to said fifth pulse to generate said second pulse; and said column logic means being alternately responsive to said first and second row logic means for generating said third pulse for each of said columns, odd and even numbered ones of said video line gate means being alternately responsive to said second pulse and the video input signal to provide interlaced scanning of said odd and even numbered rows of said coincident circuit means, and said odd and even ones of said second circuit means individually being responsive to one of said plurality of third pulses and to one of said plurality of discrete bits of the video input signal to permit one of said plurality of storage capacitors to be charged in proportion to the amplitude of one of said plurality of discrete bits of the video input signal.

Claim 16

The system of claim 10 in which is included chopper means for converting the video input signal into discrete bits, and in which each of said plurality of video gate means is provided with first and second input terminal means and an output terminal means, said first input terminal means having applied thereto a signal comprising said second pulse, said second input terminal means being connected to said chopper means, said output signal being dependent upon simultaneous application of signals to said first and second input terminals, and said output signal comprising a succession of discrete bits of the video input signal.

Claim 17

The system of claim 15 in which is included first, second, and third chopper means for respectively converting the green, blue, and red video input signal into discrete bits which are applied to each oF said color triads by a minimum of three of said video line gates, said color triads individually including at least three of said signal driver means and at least three of said signal storage means which are substantially charged simultaneously, said plurality of color triads being charged sequentially to the various amplitudes of the video signal, said predetermined portion of the video information including at least one field of multi-colored video information for displaying a natural-like image.

Claim 18

The video reproduction system of claim 15 in which each of said plurality of transistors additionally includes a gate and a source, said source of each of said transistors being connected to a common ground and said capacitor means each being provided with first and second terminAls, said first terminals thereof respectively being coupled to said gates of said transistors and to said second circuit means and said second terminals of said capacitor means respectively being coupled to said ground common to said plurality of transistors.

Claim 19

The system of claim 17 i0 which each of said second circuit means comprises silicon controlled switch means, said second circuit means having first and second input terminal means and an output terminal means, said first input terminal means having applied thereto said output signal from one of said plurality of video gate means, said second input terminal means having applied thereto one of said third pulses from said column logic means, said output terminal means individually having a signal thereon dependent upon said second circuit means simultaneously receiving one of said third pulses and said video signal and said output signals collectively constituting a plurality of various amplitude signals comprising discrete bits of the input video signal which collectively comprise the input video signal in its entirety, said output terminal means respectively being connected to said first terminals of said plurality of storage capacitor means to individually charge to the instantaneous amplitude of the input video signal and to collectively charge to various amplitudes comprising the composite input video signal in its entirety.

Claim 20

The video reproduction system of claim 18 in which said signal storage means additionally includes a plurality of solid state diode means respectively being interposed between said first terminals of said plurality of storage capacitor means and said first terminals of said plurality of resistor means for isolating said plurality of storage capacitor means from said triggering means.

Claim 21

The video reproduction system of claim 17 in which said signal storage means additionally includes a plurality of resistor means respectively having first and second terminals thereto, said first terminals thereof respectively being connected to said first terminals of said plurality of storage capacitor means and to said gates of said transistors and said second terminals thereof respectively being connected to said common ground for establishing a time constant having predetermined duration for allowing said plurality of storage capacitor means collectively to be charged consecutively to various amplitudes representing said discrete bits of a predetermined portion of the video signal, said portion including at least one field of video information, said plurality of resistor means additionally causing said luminescence pulse to be applied to said gates of said plurality of transistor means when emanated by said triggering means.

Claim 22

The video reproduction system of claim 20 in which said signal driver means additionally includes a plurality of solid state zenor diode means for enabling said plurality of storage capacitor means to rapidly discharged immediately subsequent to said luminescence means being caused to luminesce, and a plurality of parallel arranged resistance-capacitance circuit means for precluding the discharge of said plurality of capacitor means until said luminescence means are caused to luminesce, said plurality of zenor diode means and said resistance-capacitance circuit means respectively having first and second terminals thereto with said first terminal thereof being interconnected, said second terminals of said zenor diodes being connected to said common ground, and said second terminals of said resistance-capacitance circuits being connected to said triggering means.

Claim 23

The video reproduction system of claim 17 in which said storage means additionally includes a plurality of diode means respectively interposed between said second terminals of said plurality of storage capacitor means and said common ground for respectively providing first unilateral paths for current to flow while said plurality of storage capacitor means are being charged, said plurality of Diode means respectively having anodes and cathodes, said anodes respectively being connected to said second terminals of said plurality of storage capacitor means and said cathodes respectively being connected to said common ground, and a plurality of transistor means for controllably providing a second unilateral path for current to flow while said plurality of storage capacitor means are being discharged, said transistor means respectively having gate, drain, and source terminals thereto with said source terminals respectively being connected to the junction of said second terminals of said storage capacitor means and said anodes of said plurality of diode means, said drain terminals respectively being connected to said common ground, said additional pulse generated by said triggering means being a negative pulse, and said gate terminals respectively being responsive to said additional pulse.