US3750105A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data entry and display apparatus
Assignee: HP Inc
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Filing: 1972-02-14
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Granted: 1973-07-31
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Expires: 1992-02-14
Abstract
Abstract A display register and two-bit shift registers for each of a plurality of register-selecting switches are provided in addition to conventional storage registers in a computer for temporarily displaying and manipulating data thus displayed prior to its transfer into a selected register.
Inventors
- 👤 M Raynham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:24
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/01; G06F3/048; G06F3/0487; G06F3/0489
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
336 words
Digital data apparatus including a plurality of storage registers and comprising: a plurality of bit storage elements, each operable in either of two logic operating states; a switch for each bit storage element connected thereto to selectively alter the operating state of the associated bit storage element; display means coupled to said bit storage elements for indicating the operating states thereof; a pair of coupled bistate elements for each of the storage registers of the apparatus, each of said bistate elements being operable in either one of two logic states; manually-manipulatable switching means for each of the storage registers of the apparatus coupled to at least one of the pair of bistate elements to operate said bistate elements sequentially in a given logic state in response to successive manipulations of the switching means for representing the lastselected storage register and the newly selected storage register; indicator means coupled to said switching means for each of the storage registers for indicating the operating logic states of a bistate element of each of said switching means; transfer gates connected to the storage registers and to the plurality of bit storage elemEnts for selectively transferring data signals indicative of the logic states of the elements and registers between the bit storage elements and a selected storage register; and circuit means coupling the pairs of bistate elements to said transfer gates for controlling the transfer of data signals therethrough between the bit storage elements and the storage registers selected in response to the logic state of at least one bistate element associated with the switching means for a selected storage register, said circuit means including coupling circuitry to at least the bistate elements of the switching means for two selected registers to control the transfer of data signals from the plurality of bit storage elements to the last-selected storage register and to transfer data signals into the bit storage elements from a different, newly selected register in response to manual manipulation of the switching means for said newly selected register.
Claim 2
Dependent Claim
336 words
Digital data apparatus including a plurality of storage registers and comprising: a plurality of bit storage elements, each operable in either of two logic operating states; a switch for each bit storage element connected thereto to selectively alter the operating state of the associated bit storage element; display means coupled to said bit storage elements for indicating the operating states thereof; a pair of coupled bistate elements for each of the storage registers of the apparatus, each of said bistate elements being operable in either one of two logic states; manually-manipulatable switching means for each of the storage registers of the apparatus coupled to at least one of the pair of bistate elements to operate said bistate elements sequentially in a given logic state in response to successive manipulations of the switching means for representing the lastselected storage register and the newly selected storage register; indicator means coupled to said switching means for each of the storage registers for indicating the operating logic states of a bistate element of each of said switching means; transfer gates connected to the storage registers and to the plurality of bit storage elemEnts for selectively transferring data signals indicative of the logic states of the elements and registers between the bit storage elements and a selected storage register; and circuit means coupling the pairs of bistate elements to said transfer gates for controlling the transfer of data signals therethrough between the bit storage elements and the storage registers selected in response to the logic state of at least one bistate element associated with the switching means for a selected storage register, said circuit means including coupling circuitry to at least the bistate elements of the switching means for two selected registers to control the transfer of data signals from the plurality of bit storage elements to the last-selected storage register and to transfer data signals into the bit storage elements from a different, newly selected register in response to manual manipulation of the switching means for said newly selected register.
Claim 3
Dependent Claim
93 words
Digital data apparatus as in claim 1 wherein said circuit means includes control circuitry connected to transfer data signals to the plurality of bit storage elements from a storage register represented by the last-selected storage register logic state of a bistate element of the switching means for such storage register in response to manual manipulation of such switching means that establishes a logic state in one of the pair of bistate elements of such switching means which is indicative of the newly selected storage register being the same as the last-selected storage register.
Claim 4
Dependent Claim
57 words
Digital data apparatus as in claim 1 wherein said indicator means includes a visual display element for each of said switching means connected to one of the pair of bistate elements associated with said switching means for controlling the visual indication provided thereby in response to the logic operating state representative of the newly selected storage register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |