US3750040A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor delay line driver
Assignee: United States Department of the Navy
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Filing: 1972-06-21
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Granted: 1973-07-31
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Expires: 1992-06-21
Abstract
Abstract The invention disclosed herein relates to a transistor current amplifier usable as a delay line driver. The current amplifier incorporates a high gain amplifier including a transistor, a Field Effect Transistor (FET), and two Darlington-connected transistors providing the bias current through the resistor for the first transistor and feedback current through the resistor.
Inventors
- 👤 J Weir
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:22
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/345; H03F3/3455
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
186 words
An improved precision current amplifier having low input impedance and high output impedance capabilities comprising: a. first and second input terminals; b. a resistive element coupled across said input terminals; c. a first transistor having first base, emitter, and collector terminals, said first base terminal connected to said first input terminal, and said first emitter terminal connected to said second input terminal; d. a second transistor having second base, emitter, and collector terminals, said second base terminal connected to said first collector terminal and said second collector terminal connected to said first collector terminal; e. a third transistor having a third base, emitter, and, collector terminals said third base terminal connected to said first collector terminal; f. a fourth transistor having fourth base, emitter, and collector terminals, said fourth base terminal connected to said third emitter terminal, said fourth emitter terminal connected to said first base terminal, said fourth collector terminal connected to said third collector terminal; and g. first and second output terminals, said first terminal connected to said second emitter terminal and said second output terminal connected to said third and fourth collector terminals.
Claim 2
Dependent Claim
186 words
An improved precision current amplifier having low input impedance and high output impedance capabilities comprising: a. first and second input terminals; b. a resistive element coupled across said input terminals; c. a first transistor having first base, emitter, and collector terminals, said first base terminal connected to said first input terminal, and said first emitter terminal connected to said second input terminal; d. a second transistor having second base, emitter, and collector terminals, said second base terminal connected to said first collector terminal and said second collector terminal connected to said first collector terminal; e. a third transistor having a third base, emitter, and, collector terminals said third base terminal connected to said first collector terminal; f. a fourth transistor having fourth base, emitter, and collector terminals, said fourth base terminal connected to said third emitter terminal, said fourth emitter terminal connected to said first base terminal, said fourth collector terminal connected to said third collector terminal; and g. first and second output terminals, said first terminal connected to said second emitter terminal and said second output terminal connected to said third and fourth collector terminals.
Claim 3
Dependent Claim
22 words
The improved precision current amplifier of claim 1 wherein said first and second input terminals are connected across a current load device.
Claim 4
Dependent Claim
14 words
The device of claim 2 wherein said second transistor is a field effect transistor.
Claim 5
Dependent Claim
17 words
The device of claim 3 wherein said first, third and fourth transistors are high Beta type transistors.
Claim 6
Dependent Claim
16 words
The device of claim 4 wherein said output terminals are connected to a delay line device.
Claim 7
Dependent Claim
18 words
The device of claim 5 wherein said third and fourth transistors are connected in a Darlington type configuration.
References Cited (Backward Citations)
US3214705A
Cited
US3555442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |