Apparatus for multiplying binary signals based on the binomial theorem

Claim 2

A multiplier for multiplying A times B, where A and B are numbers, said numbers being represented by first and second binary signal sets, respectively, said multiplier comprising: first data processor means for processing said first and second binary signal sets to derive a third binary signal set representative of (A+B)2; second data processor means for processing said first and second binary signal sets to derive a fourth binary signal set representative of A2+B2; and third data processor means for processing said third and fourth binary signal sets to derive a fifth binary signal set representative of (A+B)2-(A2+B2).

Claim 3

Apparatus according to claim 1 further including means for dropping the least significant bit from said fifth binary signal set.

Claim 4

Apparatus according to claim 1 wherein said third data processor means comprises first complement means connected to said first data processor for reversing the binary values of each bit in said third binary signal set; first adder means connected to said first complement means and to said second data processor means for processing said fourth binary signal set and the reversed-bit third binary signal set to derive a binary output signal set representative of the sum of the numbers represented by said fourth binary signal set and said reversed-bit third binary set; and second complement means connected to said first adder means for reversing the binary values of each bit in said binary output signal set.

Claim 5

Apparatus according to claim 3 further including means for dropping the least significant bit from said fifth binary signal set.

Claim 6

Apparatus according to claim 3 wherein said first data processor means comprises second adder means for receiving said first and second binary signal sets, said second adder means processing said first and second signal sets to derive a binary signal set representative of the sum of A and B, and first squaring means connected to said second adder means for processing the binary signal set output of said first adder means to derive said third binary signal set.

Claim 7

Apparatus according to claim 5 wherein said second data processor means comprises second squaring means for processing said first binary signal set to derive a binary signal set representative of A2, third squaring means for processing said second binary signal set to derive a binary signal set representative of B2, and third adder means for processing the binary signal sets from said second and third squaring means to derive said fourth binary signal set.

Claim 8

Apparatus according to claim 6 wherein said first, second and third squaring means are gated squaring devices.

Claim 9

Apparatus according to claim 1 wherein said first data processor means comprises first adder means for receiving said first and second binary signal sets, said first adder means processing said first and second signal sets to derive a binary signal set representative of the sum of A and B, and first squaring means connected to said first adder means for processing the binary signal set output of said first adder means to derive said third binary signal set.

Claim 10

Apparatus according to claim 1 wherein said second data processor means comprises first squaring means for processing said first binary signal set to derive a binary signal set representative of A2, second squaring means for processing said second binary signal set to derive a binary signal set representative of B2, and first adder means for processing the binary signal sets from said first and second squaring means to derive said fourth binary signal set.

Claim 11

Apparatus for multiplying A times B, where A and B are numbers, said numbers being represented by first and second binary signal sets respectively, each of said first and second binary signal sets havinG n bits where n is an even whole number, said apparatus comprising: first segregating means for segregating said first binary signal set into A1 and A2 binary signal sets each having m bits, where m n/2, said A1 signal set comprising the m most significant bits of said first binary signal set and said A2 signal set comprising the m least significant bits of said first binary signal set; second segregating means for segregating said second binary signal set into B1 and B2 binary signal sets each having m bits, said B1 signal set comprising the m most significant bits of said second binary signal set and said B2 signal set comprising the m least significant bits of said second binary signal set; first data processor means for processing said A1 and B1 signal sets to derive a (A1+B1)2 binary signal set representative of the square of the sum of the numbers represented by said A1 and B1 signal sets; second data processor means for processing said A1 and B1 signal sets to derive a (A12+B12) binary signal set representative of the sum of the squares of the numbers represented by said A1 and B1 signal sets; third data processor means for processing said A2 and B2 signal sets to derive a (A2+B2)2 binary signal set representative of the square of the sum of the numbers represented by said A2 and B2 signal sets; fourth data processor means for processing said A2 and B2 signal sets to derive a (A22+B22) binary signal set representative of the sum of the squares of the numbers represented by said A2 and B2 signal sets; fifth data processor means for processing said A1 and B2 signal sets to derive a (A1+B2)2 binary signal set representative of the square of the sum of the numbers represented by said A1 and B2 signal sets; sixth data processor means for processing said A1 and B2 signal sets to derive a (A12+B22) binary signal set representative of the sum of the squares of the numbers represented by said A1 and B2 signal sets; seventh data processor means for processing said A2 and B1 signal sets to derive a (A2+B1)2 binary signal set representative of the square of the sum of the numbers represented by said A2 and B1 signal sets; eighth data processor means for processing said A2 and B1 signal sets to derive a (A22+B12) binary signal set representative of the sum of the squares of the numbers represented by said A2 and B1 signal sets; ninth data processor means for processing said (A12+B12) and (A1+B1)2 signal sets to derive an (A1B1) binary signal set representative of one-half of the difference between the numbers represented by said (A1+B1)2 signal set and said (A12+B12) signal set; tenth data processor means for processing said (A22+B22) and (A2+B2)2 signal sets to derive an (A2B2) binary signal set representative of one-half of the difference between the numbers represented by said (A2+B2)2 signal set and said (A22+B22) signal set; eleventh data processor means for processing said (A1+B2)2 and (A12+B22) signal sets to derive a third binary signal set representative of the difference between the numbers represented by said (A1+B2)2 and (A12+B22) signal sets; twelfth data processor means for processing said (A2+B1)2 and (A22+B12) signal sets to derive a fourth binary signal set representative of the difference between the numbers represented by said (A2+B1)2 and (A22+B12) signal sets; first register means for deriving a fifth binary signal set having 4 m bits, the 2 m most significant bits of said fifth binary signal set comprising the 2 m least significant bits of said (A1B1) signal set and the 2 m least significant of said fifth signal set comprising the 2 m least significant bits of said (A2B2) signal set; second register means for positively shifting said third binary signal set m-1 bits to derive a sixth binary signal set representative of 2m 1 times said third binary signal set; third register means for positively shifting said fourth binary signal set m-1 bits to derive a seventh binary signal representative of 2m 1 times said fourth binary signal set; and means for processing said fifth, sixth and seventh binary signal sets to derive an output binary signal set representative of the sum of the numbers represented by said fifth, sixth and seventh sets.

Claim 12

Apparatus for multiplying A times B, where A and B are numbers, said numbers being represented by first and second binary signal sets respectively, each of said first and second binary signal sets havinG n bits where n is an even whole number, said apparatus comprising: first segregating means for segregating said first binary signal set into A1 and A2 binary signal sets each having m bits, where m n/2, said A1 signal set comprising the m most significant bits of said first binary signal set and said A2 signal set comprising the m least significant bits of said first binary signal set; second segregating means for segregating said second binary signal set into B1 and B2 binary signal sets each having m bits, said B1 signal set comprising the m most significant bits of said second binary signal set and said B2 signal set comprising the m least significant bits of said second binary signal set; first data processor means for processing said A1 and B1 signal sets to derive a (A1+B1)2 binary signal set representative of the square of the sum of the numbers represented by said A1 and B1 signal sets; second data processor means for processing said A1 and B1 signal sets to derive a (A12+B12) binary signal set representative of the sum of the squares of the numbers represented by said A1 and B1 signal sets; third data processor means for processing said A2 and B2 signal sets to derive a (A2+B2)2 binary signal set representative of the square of the sum of the numbers represented by said A2 and B2 signal sets; fourth data processor means for processing said A2 and B2 signal sets to derive a (A22+B22) binary signal set representative of the sum of the squares of the numbers represented by said A2 and B2 signal sets; fifth data processor means for processing said A1 and B2 signal sets to derive a (A1+B2)2 binary signal set representative of the square of the sum of the numbers represented by said A1 and B2 signal sets; sixth data processor means for processing said A1 and B2 signal sets to derive a (A12+B22) binary signal set representative of the sum of the squares of the numbers represented by said A1 and B2 signal sets; seventh data processor means for processing said A2 and B1 signal sets to derive a (A2+B1)2 binary signal set representative of the square of the sum of the numbers represented by said A2 and B1 signal sets; eighth data processor means for processing said A2 and B1 signal sets to derive a (A22+B12) binary signal set representative of the sum of the squares of the numbers represented by said A2 and B1 signal sets; ninth data processor means for processing said (A12+B12) and (A1+B1)2 signal sets to derive an (A1B1) binary signal set representative of one-half of the difference between the numbers represented by said (A1+B1)2 signal set and said (A12+B12) signal set; tenth data processor means for processing said (A22+B22) and (A2+B2)2 signal sets to derive an (A2B2) binary signal set representative of one-half of the difference between the numbers represented by said (A2+B2)2 signal set and said (A22+B22) signal set; eleventh data processor means for processing said (A1+B2)2 and (A12+B22) signal sets to derive a third binary signal set representative of the difference between the numbers represented by said (A1+B2)2 and (A12+B22) signal sets; twelfth data processor means for processing said (A2+B1)2 and (A22+B12) signal sets to derive a fourth binary signal set representative of the difference between the numbers represented by said (A2+B1)2 and (A22+B12) signal sets; first register means for deriving a fifth binary signal set having 4 m bits, the 2 m most significant bits of said fifth binary signal set comprising the 2 m least significant bits of said (A1B1) signal set and the 2 m least significant of said fifth signal set comprising the 2 m least significant bits of said (A2B2) signal set; second register means for positively shifting said third binary signal set m-1 bits to derive a sixth binary signal set representative of 2m 1 times said third binary signal set; third register means for positively shifting said fourth binary signal set m-1 bits to derive a seventh binary signal representative of 2m 1 times said fourth binary signal set; and means for processing said fifth, sixth and seventh binary signal sets to derive an output binary signal set representative of the sum of the numbers represented by said fifth, sixth and seventh sets.

Claim 13

Apparatus according to claim 10 wherein said eleventh data processor means includes first inverter means for reversing the binary value of each bit of said (A12+B22) binary signal set to derive an (A12+B22) binary signal set, and first adder means for adding in binary said (A1+B2)2 and (A12+B22) binary signal sets to derive a (2A1B2- 1) binary signal set representative of a number equal to the sum of the numbers represented by said (A1+B2)2 and (A12+B22) binary signal sets; and said twelfth data processor means includes second inverter means for reversing the binary value of each bit of said (A2+B12) binary signal set to derive an (A22+B12) binary signal set, and second adder for adding in binary said (A2+B1)2 and (A22+B12binary signal sets and a binary signal set representative of decimal 2 to derive a (2A2B1+1) binary signal set representative of a number equal to the sum of 2 plus the numbers represented by said (A2+B1)2 and (A22+B12) binary signal sets; said second register means processing said (2A1B2-1) binary signal set and said fifth binary signal set to derive a (A1B1 X 22m+A2B2+A1B2 X 2m-2m 1) binary signal set representative of a number equal to 2m 1 times the number represented by said (2A1B2-1) binary signal set plus the number represented by said fifth binary signal set; and said third register means and last-named means processing said (2A2B1+1) binary signal and said (A1B1 X 22m+A2B2+A1B2 X 2m-2m 1) binary signal set to derive a AB binary signal set representative of a number equal to 2m 1 times the number represented by said (2A2B1+1) binary signal set plus the number represented by said (A1B1 X 22m+A2B2+A1B2 X 2m-2m 1) binary signal set.

Claim 14

Apparatus according to claim 10 wherein said ninth data processor means comprises seCond inverter means for reversing the binary value of each bit of said (A1+B1)2 signal set to derive a (A1+B1)2 binary signal set; thirteenth data processor means for processing said (A12+B12) and (A1+B1)2 signal sets to derive a (A12+B12)+(A1+B1)2 binary signal set representative of a number equal to the sum of the numbers represented by said (A12+B12) and (A1+B1)2 signal sets; third inverter means for reversing the binary value of each bit of said (A12+B12)+(A1+B1)2 signal set to derive a (A12+B12)+(A1+B1)2 binary signal set; and means for dropping the least significant bit from said (A12+B12)+(A1+B1)2 signal set.

Claim 15

Apparatus according to claim 10 wherein said tenth data processor means comprises second inverter means for reversing the binary value of each bit of said (A2+B2)2 signal set to derive a (A2+B2)2 binary signal set; thirteenth data processor means for processing said (A22+B22) and (A2+B2)2 signal sets to derive a (A22+B22)+(A2+B2)2 binary signal set representative of a number equal to the sum of the numbers represented by said (A22+B22) and (A2+B2)2 signal sets; third inverter means for reversing the binary value of each bit of said (A22+B22)+(A2+B2)2 signal set to derive a (A22+B22)+(A2+B2)2 binary signal set; and means for dropping the least significant bit from said (A22+B22)+(A2+B2)2 signal set.

Claim 16

Apparatus according to claim 10 wherein said ninth and tenth data processor means comprise second inverter means for reversing the binary values of each bit of said (A1+B1)2 and (A2+B2)2 signal sets to derive (A1+B1)2 and (A2+B2)2 binary signal sets, respectively; thirteenth data processor means for processing said (A12+B12) and (A1+B1)2 signal sets to derive an (A12+B12)+(A1+B1)2 binary signal set representative of a number equal to the sum of the numbers represented by said (A12+B12) and (A1+B1)2 signal sets; fourteenth data processor means for processing said (A22+B22) and (A2+B2)2 signal sets to derive a (A22+B22)+(A2+B2)2 binary signal set representative of a number equal to the sum of the numbers represented by said (A22+B22) and (A2+B2)2 signal sets; third inverter means for reversing the binary values of each bit of said (A12+B12)+(A1+B1)2 and (A22+B22)+(A2+B2)2 signal sets to derive (A12+B12)+(A1+B1)2 and (A22+B22)+(A2+B2)2 binary signal sets, respectively; and means for dropping the least significant bit from each of said (A12+B12)+(A1+B1)2 and (A22+B22)+(A2+B2)2 signal sets to derive said (A1B1) and (A2B2) binary signal sets, respectively.