US3749619A
Expired / Lapsed
US
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Method for manufacturing a semiconductor integrated circuit isolated by dielectric material
Assignee: Toshiba Corp
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Filing: 1971-06-21
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Granted: 1973-07-31
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Expires: 1991-06-21
Abstract
Abstract A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISES STEPS OF SELECTIVILY EPITAXIAL-GROWING ISLAND REGIONS ON THE UPPER SURFACE OF A SILICON SUBSTRATE, COVERING SAID ISLAND REGIONS AND THE UPPER SURFACE OF THE SUBSTRATE, FORMING A SILICON LAYER ON SAID INSULATING FILM AND ETCHING THE SILICON SUBSTRATE WITH AN ETCHANT OF HF, HNO3 AND CH3COOH WHICH SELECTIVELY ETCHES THE SILICON SUBSTRATE WITHOUT ETCHING THE ISLAND REGION.
Inventors
- 👤 T Ohashi
- 👤 Y Sumitomo
- 👤 H Muraoka
- 👤 H Tsutsumi
- 👤 T Yasui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:47
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/043; Y10S148/051; Y10S148/085
Claims Analysis
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References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |