Digital tachometer

Claim 2

A digital tachometer comprising input transducer means for generating a pulsed electrical signal indicative of the speed of a rotary member, decade counter means for receiving said electrical signal and generating a count of the pulses received during a time period, timing means including oscillator means and frequency divider means for reducing the frequency of the oscillator output and providing said time period, display means connected with said counter means for visually indicating pulse count from said counter, and control means driven by said frequency divider means and generating at the end of said time pEriod reset signals for said decade counter means and said frequency divider means and an enabling signal for said display means to receive and display the count of said decade counter means.

Claim 3

A digital tachometer as defined by claim 1 wherein said control means comprises first and second serially connected monostable multivibrators with said first multivibrator being driven by said frequency divider means and said second multivibrator being driven by said first multivibrator, said enabling signal for said display means being derived from the output of said first multivibrator and said reset signals being derived from the output of said second multivibrator.

Claim 4

A digital tachometer as defined by claim 2 wherein the pulse width at the outputs of said multivibrators is much smaller than said timing period.

Claim 5

A digital tachometer as defined by claim 2 and further including pulse shaper means interconnected between said input transducer means and said decade counter means including voltage limiting means for receiving said pulsed signal from said input transducer means and a third monostable multivibrator.

Claim 6

A digital tachometer as defined by claim 4 wherein an inhibit signal is derived from said first multivibrator for inhibiting operation of said third multivibrator at the end of said timing period.

Claim 7

A digital tachometer as defined by claim 5 and further including monitor means interconnected with said counter means and responsive to said pulse count being outside of prescribed limits.

Claim 8

A digital tachometer as defined by claim 6 wherein said monitor means includes set point means for establishing said prescribed limits and comparator means for comparing said pulse count with said prescribed limits.

Claim 9

A digital tachometer as defined by claim 7 wherein said set point means comprises first means for establishing a lower speed limit and second means for establishing an upper speed limit, each of said means including a plurality of two input exclusive OR gates, one input of each gate being connectable to said frequency divider means and the other input of each gate being connectable to said counter, switch means for connecting specific gates in accordance with the desired limit, flip-flop means, response means, means connecting said flip-flop means to said response means, and means connecting the outputs of said gates to said flip-flop means whereby said flip-flop means is tripped thereby initiating said response means when the inputs from said counter correspond to said limit.

Claim 10

A digital tachometer as defined by claim 8 wherein an inhibit signal is derived from said first multivibrator for inhibiting said flip-flop means at the end of each time period and a reset signal is derived from said first multivibrator for resetting said flip-flop means for the beginning of the next time period.

Claim 11

A digital tachometer as defined by claim 9 wherein said response means comprises an alarm.

Claim 12

A digital tachometer as defined by claim 9 wherein said response means includes feedback control means to the rotary member drive means.

Claim 13

A digital tachometer as defined by claim 1 and further including monitor means interconnected with said counter means and responsive to said pulse count being outside of prescribed limits.

Claim 14

A digital tachometer as defined by claim 12 wherein said monitor means includes set point means for establishing said prescribed limits and comparator means for comparing said pulse count with said prescribed limits.

Claim 15

A digital tachometer as defined by claim 13 wherein said set point means comprises first means for establishing a lower speed limit and second means for establishing an upper speed limit, each of said means including a plurality of two input exclusive OR gates, one input of each gate being connectable to said frequency divider means and the other input of each gate being connectable to said counter, switch means for connecting specific gates in accordance with the desired limit, flip-flop means, response means, means connecting said flip-flop means to said response means, and means connecting the outputs of said gates to said flip-flop means whereby said flip-flop means is tripped thereby initiating said response means when the inputs from said counter correspond to said limit.

Claim 16

A digital tachometer as defined by claim 14 wherein an inhibit signal is derived from said control means for inhibiting said flip-flop means at the end of each time period and a reset signal is derived from said control means for resetting said flip-flop means for the beginning of the next time period.

Claim 17

A digital tachometer comprising: a. decade counter means for receiving and counting a pulsed electrical signal; b. timing means including an oscillator and a frequency divider means for providing a time period; c. control means driven by said frequency divider means for providing reset signals at the end of each said time period to said decade counter means and to said frequency divider means; d. display means connected to receive and display pulse count from said decade counter means at the end of each said time period upon receipt of an enabling signal from said control means; and e. monitor means interconnected with said counter means and responsive to said pulse being outside of prescribed limits, said monitor means including set point means for establishing said prescribed limits and comparator means for comparing said pulse count with said prescribed limits.

Claim 18

A digital tachometer comprising: a. decade counter means for receiving and counting a pulsed electrical signal; b. timing means including an oscillator and a frequency divider means for providing a time period; c. control means driven by said frequency divider means for providing reset signals at the end of each said time period to said decade counter means and to said frequency divider means; d. display means connected to receive and display pulse count from said decade counter means at the end of each said time period upon receipt of an enabling signal from said control means; and e. monitor means interconnected with said counter means and responsive to said pulse being outside of prescribed limits, said monitor means including set point means for establishing said prescribed limits and comparator means for comparing said pulse count with said prescribed limits.

Claim 19

A digital tachometer as defined by claim 16 wherein said control means comprises first and second serially connected monostable multivibrators with said first multivibrator being driven by said frequency divider means and said second multivibrator being driven by said first multivibrator, said enabling signal for said display means being derived from the output of said first multivibrator and said reset signals being derived from the output of said second multivibrator.

Claim 20

A digital tachometer as defined by claim 16 wherein said set point means comprises first means for establishing a lower speed limit and seocnd means for establishing an upper speed limit, each of said means including a plurality of two input exclusive OR gates, one input of each gate being connectable to said frequency divider means and the other input of each gate being connectable to said counter, switch means for connecting specific gates in accordance with the desired limit, flip-flop means, response means, means connecting said flip-flop means to said response means, and means connecting the outputs of said gates to said flip-flop means whereby said flip-flop means is tripped thereby initiating said response means when the inputs from said counter correspond to said limit.