US3748498A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low voltage quasi static flip-flop
Assignee: American Microsystems Holding Corp
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Filing: 1972-07-27
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Granted: 1973-07-24
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Expires: 1992-07-27
Abstract
Abstract An integrated circuit providing a quasi static flip-flop function that is operable by a relatively low voltage source and requires only a single clock pulse. A pair of cross-connected latch transistors are each connected through a separate node to a load device between a power source and ground. Each node is connected through a first lead containing which is gate connected to a capacitor and it is also connected through a pair of resistor elements to the same capacitor. Between each pair of resistor elements is a second lead connected to the first lead and to ground through a transistor whose gate is connected to a single clock.
Inventors
- 👤 K Hoffmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:23
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
178 words
A quasi-static flip-flop circuit comprising: a pair of latch transistors, each connected at one terminal to ground and at another terminal to one of a pair of junctions and means cross-connecting their gates to said junctions; a pair of load devices each inter-connecting one said latch transistor with a power source; a pair of capacitors, each connected between one said junction and ground; two pairs of resistive elements, each pair being connected in series between one said capacitor and its connected junction; a pair of first lead members, each connected to one said junction and a pair of second lead members each connected to a terminal between one said pair of resistive elements; a pair of switching transistors, each being source-drain connected in one of said first lead members and means connecting the gate of each said switching transistor to one of said capacitors; lead means for connecting said first and second lead members to ground; switching means in said lead means and a single phase clocking pulse means connected to said switching means for operating said circuit.
Claim 2
Dependent Claim
178 words
A quasi-static flip-flop circuit comprising: a pair of latch transistors, each connected at one terminal to ground and at another terminal to one of a pair of junctions and means cross-connecting their gates to said junctions; a pair of load devices each inter-connecting one said latch transistor with a power source; a pair of capacitors, each connected between one said junction and ground; two pairs of resistive elements, each pair being connected in series between one said capacitor and its connected junction; a pair of first lead members, each connected to one said junction and a pair of second lead members each connected to a terminal between one said pair of resistive elements; a pair of switching transistors, each being source-drain connected in one of said first lead members and means connecting the gate of each said switching transistor to one of said capacitors; lead means for connecting said first and second lead members to ground; switching means in said lead means and a single phase clocking pulse means connected to said switching means for operating said circuit.
Claim 3
Dependent Claim
17 words
The circuit as described in claim 1 wherein said resistive elements are depletion mode MOS transistor elements.
Claim 4
Dependent Claim
17 words
The circuit as described in claim 1 wherein said resistive elements all have the same resistance value.
Claim 5
Dependent Claim
32 words
The circuit as described in claim 1 including an auxiliary resistive element in each of said second lead members between a terminal, between a pair of resistor elements and said lead means.
Claim 6
Dependent Claim
17 words
The circuit as described in claim 4 wherein each said auxiliary resistive element is an MOS transistor.
Claim 7
Dependent Claim
36 words
The circuit as described in claim 1 wherein at least one of each said pair of resistive elements is a depletion mode MOS device whose gate is connected to the inversion of said clocking pulse means.
Claim 8
Dependent Claim
34 words
The circuit as described in claim 6 wherein said lead means is a single lead member connected to ground and containing a source-drain connected transistor whose gate is connected to said clocking pulse means.
Claim 9
Dependent Claim
34 words
The circuit as described in claim 4 wherein one of each said pair of resistive elements is an MOS transistor whose gates are connected to an auxiliary clocking voltage for varying their resistance value.
Claim 10
Dependent Claim
186 words
An MOS quasi-static flip flop circuit comprising: a pair of latch transistors, each connected at one terminal to ground and at another terminal to one of a pair of junctions and means cross-connecting their gates to said junctions; a pair of load transistors each inter-connecting one of said latch transistors with a power source; a pair of capacitors, each connected between one said junction and ground; a pair of resistive means each being connected between one said capacitor and its connected junction; a pair of first lead members, each connected to one of said pair of junctions and to a second junction means and containing a switching transistor whose gate is connected to one of said capacitors; a pair of second lead members each connected to one of said resistive means and to said second junction means and thereby providing a means for delaying the discharge of the capacitor so that the connected switChing transistor will enable operation of the latch transistors; means for connecting said second junction means to ground and containing a switching means connected to a clocking pulse means for operating said circuit.
Claim 11
Dependent Claim
186 words
An MOS quasi-static flip flop circuit comprising: a pair of latch transistors, each connected at one terminal to ground and at another terminal to one of a pair of junctions and means cross-connecting their gates to said junctions; a pair of load transistors each inter-connecting one of said latch transistors with a power source; a pair of capacitors, each connected between one said junction and ground; a pair of resistive means each being connected between one said capacitor and its connected junction; a pair of first lead members, each connected to one of said pair of junctions and to a second junction means and containing a switching transistor whose gate is connected to one of said capacitors; a pair of second lead members each connected to one of said resistive means and to said second junction means and thereby providing a means for delaying the discharge of the capacitor so that the connected switChing transistor will enable operation of the latch transistors; means for connecting said second junction means to ground and containing a switching means connected to a clocking pulse means for operating said circuit.
Claim 12
Dependent Claim
32 words
The circuit as described in claim 9 wherein each said resistive means comprises a pair of depletion mode MOS transistor elements, and a load transistor connected in each said second lead member.
References Cited (Backward Citations)
US3383569A
Cited
US3363115A
Cited
US3614476A
Cited
US3514765A
Cited
US3624423A
Cited
US3629612A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-23 | 1977-01-22 | 1977-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-23 | 1981-01-22 | 1981-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-23 | 1985-01-22 | 1985-07-24 | $7700.00 | Window Closed / Lapsed |