Device for determining the median number in a series of numbers

Claim 2

In a system for producing a signal representing the median number in a sequence of numbers in a number system having at Least two orders, the combination comprising: a. a source of clock pulses; b. a shift register for shifting input signals representing a first sequence of numbers of a least significant order in response to successive pulses from said clock source; c. a means for counting responsive to pulses from said clock source and connected to said shift register, said counter means counting each shift of said register until a one representing the first number in said first sequence is shifted to the last bit position of said register and further counting alternate ones stored in said register to determine the median number in said first sequence; and d. a logic circuit for receiving a second sequence of numbers of second order in said number system and for determining the least significant character in said second sequence, said logic circuit responsive to said counter for increasing its determination by one character whenever the number of pulses counted by said counter exceeds the radix of said least significant order thereby determining the second order character of the median number in said sequence of numbers having two orders.

Claim 3

A decoding system for determining the median character in a sequence of characters in a predetermined number system comprising: a. a source of clock pulses; b. a first plurality of input terminals for receiving a first set of binary signals, each binary signal in said first set representing one first order character in a number system having a first predetermined radix, said first set of signals including a first sequence of signals each having a predetermined logical state; c. a second plurality of input terminals for receiving a second set of binary signals, each binary signal in said second set representing a second order character in the set to said radix predetermined number system, said second set of signals including a second sequence having a predetermined logical state; d. a shift register connected to said first plurality of input terminals for receiving said first set of binary signals, said shift register having a bit storing device corresponding to each of the characters in said first set of binary signals, said shift register transferring each character in said first set to a bit storing device until the first character in said first sequence having said predetermined logical state is transferred to the bit storing device of said shift register corresponding to the lowest character in said first set of binary signals in response to clock pulses; e. a means for counting responsive to pulses from said clock source and connected to said shift register, said counter means counting the number of shifts in said register to transfer the first character in the first sequence having the predetermined logical state plus counting the number of alternate characters in the sequence having the predetermined logical state to determine and indicate the median character in the first sequence of characters in said first set of binary signals having the predetermined logical state; and f. a logic circuit connected to said second plurality of terminals for receiving said second set of binary signals, said logic circuit determining the lowest second order character in said second sequence in said second set of binary signals having the same predetermined logical state said logic circuit coupled to said counter means for receiving a carry signal when the total counted by said counter means exceeds said predetermined first radix, said logic circuit increasing said second order character by one in response to a carry signal.

Claim 4

A decoding system for determining the median character in a sequence of characters in a predetermined number system comprising: a. a source of clock pulses; b. a first plurality of input terminals for receiving a first set of binary signals, each binary signal in said first set representing one first order character in a number system having a first predetermined radix, said first set of signals including a first sequence of signals each having a predetermined logical state; c. a second plurality of input terminals for receiving a second set of binary signals, each binary signal in said second set representing a second order character in the set to said radix predetermined number system, said second set of signals including a second sequence having a predetermined logical state; d. a shift register connected to said first plurality of input terminals for receiving said first set of binary signals, said shift register having a bit storing device corresponding to each of the characters in said first set of binary signals, said shift register transferring each character in said first set to a bit storing device until the first character in said first sequence having said predetermined logical state is transferred to the bit storing device of said shift register corresponding to the lowest character in said first set of binary signals in response to clock pulses; e. a means for counting responsive to pulses from said clock source and connected to said shift register, said counter means counting the number of shifts in said register to transfer the first character in the first sequence having the predetermined logical state plus counting the number of alternate characters in the sequence having the predetermined logical state to determine and indicate the median character in the first sequence of characters in said first set of binary signals having the predetermined logical state; and f. a logic circuit connected to said second plurality of terminals for receiving said second set of binary signals, said logic circuit determining the lowest second order character in said second sequence in said second set of binary signals having the same predetermined logical state said logic circuit coupled to said counter means for receiving a carry signal when the total counted by said counter means exceeds said predetermined first radix, said logic circuit increasing said second order character by one in response to a carry signal.

Claim 5

The device as claimed in claim 2 wherein said logic circuit includes a counter.