Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
137 words
In a radiotelephone system having multiple frequency sepArated channels, a circuit arrangement for determining the presence of dialing information signals or signalling information signals on said channels comprising, in combination: receiver means; an evaluation circuit; switching means for cyclically switching said receiver means to said individual channels of the communication system; and means for effectively coupling each of said individual channels sequentially to said evaluation circuit for a given time interval which is short compared to the duration of the dialing information signals or the signaling information signals, said evaluation circuit having a response time less than the given time interval and being effective for detecting dialing information signals or signaling information signals, whereby the calling state of each of the individual channels is determined from the presence and absence of the dialing or signaling information signals.
Claim 2
Dependent Claim
137 words
In a radiotelephone system having multiple frequency sepArated channels, a circuit arrangement for determining the presence of dialing information signals or signalling information signals on said channels comprising, in combination: receiver means; an evaluation circuit; switching means for cyclically switching said receiver means to said individual channels of the communication system; and means for effectively coupling each of said individual channels sequentially to said evaluation circuit for a given time interval which is short compared to the duration of the dialing information signals or the signaling information signals, said evaluation circuit having a response time less than the given time interval and being effective for detecting dialing information signals or signaling information signals, whereby the calling state of each of the individual channels is determined from the presence and absence of the dialing or signaling information signals.
Claim 3
Dependent Claim
26 words
The circuit arrangement as defined in claim 1 wherein said evaluation circuit comprises a coincidence circuit means for evaluating dialing information signals or signaling information signals.
Claim 4
Dependent Claim
51 words
The circuit arrangement as defined in claim 2 wherein said switching means has a scanning frequency of fs 1/nta k . fi for k 1, 2, 3 . . . where fi 1/ti, ti being the pulse width of a bit of the dialing infomation signals or the signaling information signals.
Claim 5
Dependent Claim
27 words
The circuit arrangement as defined in claim 1 wherein said evaluation circuit comprises a squelch control circuit means having a response time less than the given interval.
Claim 6
Dependent Claim
39 words
The circuit arrangement as defined in claim 1 wherein the dialing information signals and signaling information signals are in the form of binary bits, said evaluation circuit having a response time less than the width of a single bit.
Claim 7
Dependent Claim
58 words
The circuit arrangement as defined in claim 5 wherein the binary bits representing ''''1'''' are a.c. signals of one frequency and the binary bits representing ''''0'''' are a.c. signals of another frequency, said evaluation circuit having a response time corresponding to the interval of a full wave period of whichever of the a.c. signals has the higher frequency.
Claim 8
Dependent Claim
58 words
The circuit arrangement as defined in claim 5 wherein the binary bits representing ''''1'''' are a.c. signals of one frequency and the binary bits representing ''''0'''' are a.c. signals of another frequency, said evaluation circuit having a response time corresponding to the interval of a half wave period of whichever of the a.c. signals has the higher frequency.
Claim 9
Dependent Claim
24 words
The circuit arrangement as defined in claim 6 wherein said evaluation circuit comprises coincidence circuit means responsive to zero passages of said a.c. signals.
Claim 10
Dependent Claim
24 words
The circuit arrangement as defined in claim 7 wherein said evaluation circuit comprises coincidence circuit means responsive to zero passages of said a.c. signals.