US3748386A
Expired / Lapsed
US
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Time-base error correction system
Assignee: Individual
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Filing: 1972-04-03
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Granted: 1973-07-24
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Expires: 1992-04-03
Abstract
Abstract A time-base error correction system for a video signal employing a plurality of serially connected delay lines. Circuit means are conditioned to detect the closest timing match between a reference synchronizing signal and the video signal as it appears at various points along the delay path and to connect the appropriate delay line point or junction to an output at which the correctly delayed video signal appears. Featured circuitry provides for eliminating the erroneous leading edge of a video synchronizing pulse distorted by changes in the selected delay point and for compensating for variations in d.c. offset of the video signal introduced by differential delay line path effects.
Inventors
- 👤 D Monney
- 👤 W Herzog
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:14
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/95; H04N5/14; H04N5/16; H04N5/18; H04N5/185; H04N5/92; H04N5/931
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
209 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps of said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection means, the improvement in said detection means comprising: a separate electrical flip-flop means associated with each of said taps and each having an output connected to and operating said switching means to connect the associated tap to said video output, a separate sync pulse detector connected to each tap for sensing the occurrence of said video signal waveform therewith, a permit selection pulse generator receiving said reference signal and generating a permit selection pulse in response thereto, gating means connecting each said sync pulse detector to an input of an associated flip-flop means for switching the state thereof, said gating means having a control input connected to said permit selection pulse generator for enabling said gating means in response thereto, whereby the input of said flip-flop means is responsive to an associated detection only when said gating means is enabled by a permit selection.
Claim 2
Dependent Claim
209 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps of said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection means, the improvement in said detection means comprising: a separate electrical flip-flop means associated with each of said taps and each having an output connected to and operating said switching means to connect the associated tap to said video output, a separate sync pulse detector connected to each tap for sensing the occurrence of said video signal waveform therewith, a permit selection pulse generator receiving said reference signal and generating a permit selection pulse in response thereto, gating means connecting each said sync pulse detector to an input of an associated flip-flop means for switching the state thereof, said gating means having a control input connected to said permit selection pulse generator for enabling said gating means in response thereto, whereby the input of said flip-flop means is responsive to an associated detection only when said gating means is enabled by a permit selection.
Claim 3
Dependent Claim
114 words
In the system of Claim 1, the improvement in said detection means further comprising, an inhibit select pulse generator, an OR logic gate having a separate inputs individually connected to the outputs of said flip-flops and having an output connected to and operating said inhibit pulse generator, said gating means connected and responsive to an output of said inhibit circuit pulse generator for disabling the response of each of said flip-flops to said sync pulse detectors, whereby said inhibit pulse generator is actuated once one of said flip-flops is switched and the inhibit pulse generated in response thereto operates said gating means to disable further response of the flip-flops to said sync pulse detectors.
Claim 4
Dependent Claim
191 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps between said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection of the firsT occurring video synchronizing waveform at one of said junctions following the reference timing signal, the combination with said delay lines, detection means and switching means comprising; video signal gating means interposed between said switching means and said video output, control circuit means connected to an input to said delay lines and to said detection means and being responsive to a leading edge of said video waveform at an input to said delay lines to dispose said video gating means in a gate-off condition and said control circuit means being responsive to detection of said first occurring video waveform following the reference signal to dispose said video gating means in a gate-on condition, whereby a stretched leading edge of the video synchronizing waveform is cancelled.
Claim 5
Dependent Claim
191 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps between said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection of the firsT occurring video synchronizing waveform at one of said junctions following the reference timing signal, the combination with said delay lines, detection means and switching means comprising; video signal gating means interposed between said switching means and said video output, control circuit means connected to an input to said delay lines and to said detection means and being responsive to a leading edge of said video waveform at an input to said delay lines to dispose said video gating means in a gate-off condition and said control circuit means being responsive to detection of said first occurring video waveform following the reference signal to dispose said video gating means in a gate-on condition, whereby a stretched leading edge of the video synchronizing waveform is cancelled.
Claim 6
Dependent Claim
99 words
The combination as defined in claim 3 further comprising; OR logic circuit means connected to said control circuit means having an input responsive to said detected first occurring video waveform following the reference signal and another input responsive to the video waveform appearing at an output tap of the last serially connected delay line such that said control circuit means operates to dispose said video gating means in its gate-on condition in response to either of the inputs to said OR logic means, whereby said gating means is released from its gate-off condition in the absence of said detection.
Claim 7
Dependent Claim
144 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive a video signal therethrough, detection means comparing a reference synchronizing signal with the video signal at each of a plurality of taps along said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection of the first occurring video synchronizing signal at one of said taps following the reference synchronizing signal, the combination with said delay lines, detection means and switching means comprising; AND logic means connected to said switching means and being responsive to a condition in which none of said taps are selected for connection to said video output, circuit means connected and responsive to said logic means operating said switching means to connect a predetermined one of said taps to said video output.
Claim 8
Dependent Claim
144 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive a video signal therethrough, detection means comparing a reference synchronizing signal with the video signal at each of a plurality of taps along said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection of the first occurring video synchronizing signal at one of said taps following the reference synchronizing signal, the combination with said delay lines, detection means and switching means comprising; AND logic means connected to said switching means and being responsive to a condition in which none of said taps are selected for connection to said video output, circuit means connected and responsive to said logic means operating said switching means to connect a predetermined one of said taps to said video output.
Claim 9
Dependent Claim
63 words
The combination of claim 5 in which said switching means includes a separate switch control and switch for each delay line tap, and said AND logic means comprising an AND gate having inputs connected to each of said separate switch controls and said circuit means having an output connected to and for operating one of said switches associated with one of switch controls.
Claim 10
Dependent Claim
171 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive a video signal therethrough, a detection means comparing a reference synchronizing signal with the video signal as it appears at each of a plurality of taps, and switching means connecting a selected one of said taps to an output in response to the detection of the first occurring video synchronizing signal at one of said terminal ends following the reference synchronizing signal, the combination with said delay lines, detection means and switching means comprising; an input clamping circuit connected at the input to said delay lines and being responsive to the average d.c. level of a plurality of video synchronizing signals to restore such d.c. level to a selected reference voltage, and an output d.c. clamping circuit connected at said output and being responsive to each synchronizing waveform of said video signal to clamp said output to a preselected reference voltage for the duration of the video signal period following each said synchronizing waveform.
Claim 11
Dependent Claim
171 words
In a time-base error correction system having a plurality of serially connected delay lines disposed to receive a video signal therethrough, a detection means comparing a reference synchronizing signal with the video signal as it appears at each of a plurality of taps, and switching means connecting a selected one of said taps to an output in response to the detection of the first occurring video synchronizing signal at one of said terminal ends following the reference synchronizing signal, the combination with said delay lines, detection means and switching means comprising; an input clamping circuit connected at the input to said delay lines and being responsive to the average d.c. level of a plurality of video synchronizing signals to restore such d.c. level to a selected reference voltage, and an output d.c. clamping circuit connected at said output and being responsive to each synchronizing waveform of said video signal to clamp said output to a preselected reference voltage for the duration of the video signal period following each said synchronizing waveform.
Claim 12
Dependent Claim
135 words
The combination of claim 7 wherein said output clamping circuit comprises; a comparator having one input connected to the video signal line to be clamped and another input adapted to receive a reference clamping voltAge, capacitive storage means for holding the amount of d.c. voltage correction required during the period of said video signal following each synchronizing waveform, buffer means connecting said storage means to said line, current source means connected to and for passing current to said storage means to change the amount of d.c. voltage correction held thereby, and control logic circuit means connecting an output of said comparator to said current source means and being responsive to the synchronizing waveform of the video signal for responding to the output of said comparator means to operate said current source means in accordance therewith.
Claim 13
Dependent Claim
69 words
The combination of claim 8 wherein said comparator output assumes one of two logic states depending upon the relative levels of the voltage inputs thereto, said current source means includes a positive constant current source and a negative constant current source, and said control logic circuit means operates in response to the output logic state of said comparator to turn on one or the other of said current sources.
Claim 14
Dependent Claim
44 words
The combination of claim 9 wherein said control logic includes circuitry for sensing a transition in logic state at the output of said comparator and gate means responsive to such circuitry turning off both said current sources in response to such transition of states.
Claim 15
Dependent Claim
40 words
The combination of claim 10 wherein said control logic means further comprises circuitry operating said gate means to turn off both said current sources only in response to the transition of output states of said comparator in a predetermined direction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-23 | 1977-01-22 | 1977-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-23 | 1981-01-22 | 1981-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-23 | 1985-01-22 | 1985-07-24 | $7700.00 | Window Closed / Lapsed |