Memory write circuit

Claim 2

A MOS integrated write circuit apparatus comprising: logic gating means including: a storage node; transistor circuit means being coupled to said storage node and to a first reference voltage, said transistor circuit means including means for receiving a first clocking signal, said first clocking signal conditioning said transistor circuit means to charge said storage node to said first reference voltage corresponding to a state representative of an anticipated predetermined result; transistor logic means for receiving a second clocking signal and at least first and second binary information signals, said transistor logic means being operative at the termination of said second clocking signal to logically combine said first and second binary signals and to change the state of said storage noDe in accordance with the results of logically combining said binary signals; and, transistor driver means including: transistor input means connected to said storage node for receiving said stored signal; and, transistor output means connected to said transistor input means and to first and second output terminals, said transistor output means including first and second output nodes coupled to said first and second output terminals, said transistor input means being connected to receive a third clocking signal, said transistor input means being responsive to said third clocking signal and to said state of said storage node to condition said transistor output means to charge and discharge selectively said first and second output nodes to different states in accordance with the state of said storage node so as to produce complementary output signals at said first and second output terminals representative of the result of combining said binary information signals.

Claim 3

The write circuit apparatus of claim 1 wherein said transistor logic means is connected to compare the states of said binary information signals and switch the state of said storage node, said transistor output means being conditioned by a change in state of said storage node to apply said complementary output signals corresponding to the complement of the result of comparing said states of said binary signals.

Claim 4

The write circuit apparatus of claim 1 wherein said transistor circuit means includes: a MOS device having a control and first and second output electrodes, said control electrode being connected to receive said first clocking signal, said first electrode being connected to a first reference voltage and said second electrode being connected to said storage node; and wherein said transistor logic means further includes: first and second pairs of series connected first and second MOS devices, each of said MOS devices having control, first and second output electrodes, said control electrodes of said first MOS device of said first and second pairs respectively being connected to receive the assertion and the complement of a first one of said binary information signals, and said control electrodes of said second MOS device of said first and second pairs respectively being connected to receive the assertion and complement of a second one of said binary information signals, said second electrodes of said first MOS devices being connected in common to said first electrode of said MOS device of said transistor circuit means, said first electrodes of said second MOS devices being connected to a second reference voltage; and wherein said storage node includes; capacitor means being connected to said output electrodes of said first MOS devices, said capacitor means being charged to said first reference voltage representative of said anticipated predetermined result by said MOS device of said transistor circuit means in response to said first clocking signal and said capacitor means being conditionally discharged to said second reference voltage during an interval following the termination of said second clocking signal through said first and second pairs of said MOS devices in accordance with said result of logically combining the states of said assertion and complement of said second binary information signal sampled in response to said second clocking signal.

Claim 5

The write circuit apparatus of claim 1 wherein said storage node includes capacitor means connected to said transistor circuit means and to said transistor driver means, said capacitor means being connected to store temporarily said state representative of said result.

Claim 6

The write circuit apparatus of claim 4 wherein said transistor driver means includes: first MOS transistor input switching means having control, first and second output electrodes, said control electrode being connected to said capacitor means of said storage node, said first electrode being connected to said Second output node and said second electrode being connected to receive said third clocking signal; second MOS transistor switching means having control, first and second output electrodes, said control electrode being connected to receive said second clocking signal, said second electrode being connected to a first reference voltage and said first electrode being connected to said first output node; said first output node including first capacitor means connected to said first output terminal and being charged by said second MOS transistor switching means to said first reference voltage in response to said second clocking signal; third MOS transistor switching means having control, first and second output electrodes, said control electrode being connected to said first electrode of said first transistor switching means, said first electrode being connected to said second reference voltage and said second electrode being connected to a first electrode of said second transistor switching means; and said second output node including second capacitor means connected to said control electrode of said third MOS transistor switching means and being connected to be discharged by said second MOS transistor means to said second reference voltage in response to said first clocking signal; said first transistor switching means in response to said third clocking signal being conditioned by said stored signal on said storage node to switch the state of said first and second output terminals by selectively discharging said first capacitor means to said first reference voltage through said third transistor switching means and selectively charging said second capacitor means to said first reference voltage by said first transistor in accordance with the state of said storage node.

Claim 7

The write circuit apparatus of claim 5 wherein said capacitor means of said storage node includes the intrinsic capacitance of said control electrode of said first MOS transistor switching means and said first capacitor means of said first output node includes the intrinsic capacitance of said control electrode of said third MOS transistor switching means.

Claim 8

The write circuit apparatus of claim 5 wherein said apparatus further includes buffer circuit means connected to said transistor circuit driver means and to an input/output bus of a storage unit, said buffer circuit means including: first MOS transistor means having control, first and second output electrodes, said control electrode being connected to said first output terminal and said second electrode being connected to receive said third clocking signal; capacitor means connected between said control and first electrodes of said first MOS transistor means; second MOS transistor means including control, first and second output electrodes, said second electrode being connected to said first electrode of said first transistor means, said first electrode being connected to said second reference voltage and said control electrode being connected to said second output terminal; and, third MOS transistor means including control, first and second output electrodes, said first electrode being connected to said first and second electrodes of said first and second MOS transistor means respectively, said control electrode being connected to receive said third clocking signal, said capacitor means being charged to said first reference voltage together with said first capacitor means of said first output node by said second MOS transistor switching means of said transistor output means in response to said second clocking signal switching said first MOS transistor means into conduction and, said first and third MOS transistor switching means being conditioned by one set of states of said complementary output signals from said first and second output nodes to enable the charging said input/output bus to said first reference voltage in response to said third clocking signal and saId second and third MOS transistor switching means being conditioned by another set of states of said complementary output signals from said output nodes to enable the discharging said input/output bus to said second reference voltage whereby the state of said input/output bus at the termination of said third clocking signal represents the binary information to be stored by said storage unit.

Claim 9

The write circuit apparatus of claim 7 wherein said first capacitor means of said first output node includes the intrinsic capacitance of said control electrode of said first MOS transistor means.

Claim 10

Write circuit apparatus for use in an addressable semiconductor memory store for writing binary ONE and binary ZERO information into an addressed memory cell of said store, said write circuit apparatus comprising: logic gating means including: transistor circuit means for receiving a first clocking signal; storage node capacitor means connected to said transistor means and being conditioned by said transistor circuit means during an occurrence of said first clocking signal to store a signal representative of a predetermined result; transistor logic means connected to said capacitor means, said transistor logic means including means for receiving a second clocking signal and transistor gating means for receiving at least first and second binary input signals, said transistor gating means being operative to logically combine said first and second signals in response to the termination of said second clocking signal and said transistor gating means being connected to change the state of said storage node capacitor means in accordance with the result of logically combining said signals; and, transistor driver means including: transistor input means connected to said capacitor means for receiving said stored signal; and, transistor output means connected to said transistor input means and said output means including transistor switching means coupled to a first and a second output terminal, said transistor input means being connected to receive a third clocking signal and being operative in response to said third clocking signal to condition said transistor switching means to be switched so as to apply complementary output signals to said first and second output terminals representative of binary information in accordance with the state of said stored signal.

Claim 11

Write circuit apparatus for use in an addressable semiconductor memory store for writing binary ONE and binary ZERO information into an addressed memory cell of said store, said write circuit apparatus comprising: logic gating means including: transistor circuit means for receiving a first clocking signal; storage node capacitor means connected to said transistor means and being conditioned by said transistor circuit means during an occurrence of said first clocking signal to store a signal representative of a predetermined result; transistor logic means connected to said capacitor means, said transistor logic means including means for receiving a second clocking signal and transistor gating means for receiving at least first and second binary input signals, said transistor gating means being operative to logically combine said first and second signals in response to the termination of said second clocking signal and said transistor gating means being connected to change the state of said storage node capacitor means in accordance with the result of logically combining said signals; and, transistor driver means including: transistor input means connected to said capacitor means for receiving said stored signal; and, transistor output means connected to said transistor input means and said output means including transistor switching means coupled to a first and a second output terminal, said transistor input means being connected to receive a third clocking signal and being operative in response to said third clocking signal to condition said transistor switching means to be switched so as to apply complementary output signals to said first and second output terminals representative of binary information in accordance with the state of said stored signal.

Claim 12

The write circuit apparatus of claim 9 further including at least one buffer circuit means comprising: first MOS transistor means having control, first and second output electrodes, said control electrode being connected to said first output terminal and said second electrode being connected to receive said third clocking signal; capacitor means connected between said control and first electrodes of said first MOS transistor means; second MOS transistor means including control, first and second output electrodes, said second electrode being connected to said first electrode of said first transistor means, said first electrode being connected to said second reference voltage and said control electrode being connected to said second output terminal; and, third MOS transistor means including control, first and second output electrodes, said first electrode being connected to said first and second electrodes of said first and second MOS transistor means respectively, said control electrode being connected to receive said third clocking signal, said capacitor means being charged to said first reference voltage together with said first capacitor means by said second MOS transistor switching means of said transistor output means in response to said second clocking signal switching said first MOS transistor means into conduction and, said first and third MOS transistor switching means being conditioned by one set of states of said complementary output signals to enable the charging said input/output bus to said first reference voltage in respoNse to said third clocking signal and said said second and third MOS transistor switching means being conditioned by another set of states of said complementary output signals to enable the discharging said input/output bus to said second reference voltage whereby the state of said input/output bus at the termination of said third clocking signal represents the binary information to be stored in said addressed memory cell.

Claim 13

The write circuit apparatus of claim 1 further including: a plurality of control transistor switching means, a first one of said control transistor means being connected to said storage node and to said second reference voltage,; and a second one of said control transistor switching means connected to a predetermined one of said output nodes of said transistor output means and to said second reference voltage; each of said first and second ones of said control transistor switching means being connected to receive a first bilevel mode control signal, said first and second control transistor means being responsive to one level of said control signal to discharge said storage node and said predetermined one of output nodes respectively to said second reference voltage inhibiting the operation of said transistor logic means and said transistor output means.

Claim 14

The write circuit apparatus of claim 11 wherein a third and a fourth one of said plurality of said control transistor means are connected in parallel with said first and said second ones of said control transistor switching means respectively, said third and fourth ones of said control transistor means each being connected to receive a second bilevel select control signal, said third and fourth ones of said control transistor means being responsive to one level said second control signal to discharge said storage node and output node respectively inhibiting said operation of said transistor logic means and said transistor output means.

Claim 15

The write circuit of claim 11 wherein each of said control transistor switching means includes: at least one MOS transistor having control, first and second output electrodes, said control electrode being connected to receive said bilevel control signal and said first electrode being connected to said second reference voltage; said second output electrode of MOS transistor of said first one of said plurality of control transistor switching means being connected to said storage node; said second output electrode of said MOS transistor of said second one of said plurality of control transistor switching means being connected to said predetermined one of said output nodes, and each of said MOS transistors being responsive to said one level of said bilevel signal to switch into conduction and provide a conduction path between said first and second output electrodes for discharging said storage node and said one predetermined of said output nodes to said second reference voltage.

Claim 16

The write circuit of claim 13 wherein each of said MOS transistors has a predetermined width to length ratio, said predetermined width to length ratio being selected to enable said transistors to discharge said storage node and said predetermined one of said output nodes to said second reference voltage within a predetermined time interval after said bilevel control signal switches to said one level.

Claim 17

The write circuit of claim 13 wherein said bilevel control signal is a low level signal and each of said MOS transistors has a predetermined width to length ratio, said predetermined width to length ratio being selected to enable said transistors to discharge said storage node and said predetermined one of said output nodes to said second reference voltage within a predetermined time interval after said bilevel control signal switches to said one level.

Claim 18

The write circuit apparatus of claim 9 wherein said transistor logic means includes: first and second pairs of series connected first and second MOS devices, each of said MOS devices having control, first and second output electrodes, said control electrodes of said first MOS device of said first and second pairs respectively being connected to receive the assertion and the complement of a first one of said binary information signals, said control electrodes of said second MOS devices of said first and second pairs respectively being connected to receive the assertion and complement of a second one of said binary information signals, said second electrodes of said first MOS devices being connected in common to said storage node capacitor means and said first and second MOS devices of said first and second pairs being conditioned by said binary information signals to provide alternate conductive paths to discharge conditionally said capacitor means to said second reference voltage at the termination of said second clocking signal whereby said capacitor means stores a signal representing said result of logically combining said binary information signals.

Claim 19

The write circuit apparatus of claim 16 wherein each of said second MOS devices has an intrinsic control electrode capacitance for temporarily storing signals and wherein said transistor logic means further includes input means comprising: a first clocked MOS device having control, first and second output electrodes, said control electrode being connected to receive the assertion of said second one of said binary information signals, said second output electrode being connected to receive said second clocking signal; a second clocked MOS device having control, first and second output electrodes, said control electrode being connected to receive said first clocking signal, said first electrode being connected to said control electrode and said first electrode of said second and first MOS device respectively of said first and second pairs; and, circuit means for applying said second clocking signal to said first electrodes of said second MOS device of said first and second pairs, said second clocked MOS device being conditioned by said first clocking signal to provide a conductive path between said first and second output electrodes to charge said intrinsic capacitance of said second MOS device of said first pair to said first reference voltage, said first clocked MOS device of said input means being conditioned by said second clocking signal to provide a conductive path between said first and second electrodes to charge said intrinsic capacitance of said second MOS device of said first pair to said first reference voltage and said first clocked MOS device at the termination of said second clocking signal being conditioned by said second binary signal to provide a conductive path between said first and second electrodes to discharge selectively said intrinsic capacitance of said second MOS device of said second pair to said second reference voltage in accordance with the state of said second binary information signal, said second MOS device of said second pair being conditioned by the state of said intrinsic capacitance to provide a conductive path between said first and second output electrodes to discharge said intrinsic capacitance of said second MOS device of said first pair thereby producing said assertion and complement of said second binary information signal.

Claim 20

The write circuit apparatus of claim 17 wherein said input circuit means is connected to receive said second binary information signal from said semiconductor memory store and wherein said first MOS devices of said first and second pairs are connected to receive said assertion and complement of said first binary information signal.

Claim 21

The write circuit apparatus of claim 17 wherein said assertion and complement of said first information signal are low level signals and wherein the gain of each of said first MOS devices of said first and second pairs is selected so as to respond to said signals within a predetermined time period.

Claim 22

The wRite circuit apparatus of claim 17 wherein each of said MOS devices are P channel enhancement type transistors.

Claim 23

The write circuit apparatus of claim 17 wherein said first and second pairs of MOS devices selectively discharge said storage node capacitor means to said second reference voltage when said first and second binary information signals have the same states thereby producing a stored signal on said capacitor means representative of the result of an exclusive OR operation performed on said binary information signals.

Claim 24

The write circuit apparatus of claim 21 wherein said second binary signal represents the complement of the binary information signal to be logically combined and said first and second pairs of MOS devices selectively discharge said storage node capacitor means to said second reference voltage when said first and second binary information signals have the same states thereby producing a stored signal on said storage node capacitor means representative of the result of the complement of said exclusive OR operation.