Adaptive equalizer for digital information

Claim 2

A digital adaptive equalizer system which comprises: a. a source of digital information, b. an electronically controllable equalizer having an input to which said source is coupled and having a digital information output, c. a quality determining means coupled to said output of said equalizer for producing a quality signal which represents the amount of time the digital information in said equalizer output is in transition from one state to another, and d. a maximizing circuit means having an input coupled to the output of said quality determining means, and having output means coupled to said equalizer for controlling said equalizer to improve the quality of digital information output therefrom.

Claim 3

The equalizer system of claim 1 in which said digital information is in binary form.

Claim 4

means for converting the output taken across the connection point of the two series resistors and the connection point of said LC circuit and said switched resistors to an unbalanced line output, and

Claim 5

means for converting the output taken across the connection point of the two series resistors and the connection point of said LC circuit and said switched resistors to an unbalanced line output, and

Claim 6

said switched resistors each being of different values, the larger value resistors being of a value which is equal to an integer power of two times the value of the smallest resistor and said switched resistors each having electronically controlled switches to place them in out out of the bridge circuit; c. a quality determining means having an input coupled to the digital information output of said equalizer for producing a voltage which represents the quality of digital information at the said output of said equalizer, d. a maximizing circuit means connected to the output of said quality determining means and to said equalizer for adjusting said equalizer to obtain a value for said quality voltage representative of maximum quality of digital information at the output of said equalizer, said maximizing circuit means including up-down counters having binary outputs coupled to and controlling said electronically controlled switches.

Claim 7

said switched resistors each being of different values, the larger value resistors being of a value which is equal to an integer power of two times the value of the smallest resistor and said switched resistors each having electronically controlled switches to place them in out out of the bridge circuit; c. a quality determining means having an input coupled to the digital information output of said equalizer for producing a voltage which represents the quality of digital information at the said output of said equalizer, d. a maximizing circuit means connected to the output of said quality determining means and to said equalizer for adjusting said equalizer to obtain a value for said quality voltage representative of maximum quality of digital information at the output of said equalizer, said maximizing circuit means including up-down counters having binary outputs coupled to and controlling said electronically controlled switches.

Claim 8

The equalizer system of claim 1 in which said source of digital information produces digital information in the form of a digitally modulated carrier, said quality determining means includes a demodulator having an input connected to said output of said equalizer for demodulating the carrier to obtain a digital signal, and said quality determining means also includes a quality determinator having an input connected to the output of said demodulator and an output connected to said maximizing circuit means.

Claim 9

A digital adaptive equalizer system which comprises: a. a source of digital information, b. an electronically controllable equalizer having a plurality of stages and a first input to which said source is coupled, and having an output for an equalized signal, c. a quality determining means coupled to said equalizer output for determining the quality of the equalized signal, and having an output, d. a maximizing circuit means connected to the output of said quality determining means and having an output coupled to a second input of said equalizer for periodically adjusting each stage of said electronically controllable equalizer and including sequencing means for causing the adjustments to be made to only one of said stages at a time and for causing each of said stages to be adjusted in turn.

Claim 10

A digital adaptive equalizer system which comprises: a. a source of digital information, b. an electronically controllable equalizer having a plurality of stages and a first input to which said source is coupled, and having an output for an equalized signal, c. a quality determining means coupled to said equalizer output for determining the quality of the equalized signal, and having an output, d. a maximizing circuit means connected to the output of said quality determining means and having an output coupled to a second input of said equalizer for periodically adjusting each stage of said electronically controllable equalizer and including sequencing means for causing the adjustments to be made to only one of said stages at a time and for causing each of said stages to be adjusted in turn.

Claim 11

The equalizer system of claim 4 in which said maximizing circuit means includes: a. a low frequency oscillator; b. a pulse dividing circuit connected to the output of said oscillator, c. a plural state cycle having one input and a plurality of outputs, only one output at a time being ''''on'''' and the ''''on'''' state changing sequentially among the outputs each time a signal is received at the input, said means having an input connected to the output of said pulse dividing circuit, and having a plurality of outputs, and d. a plurality of logic gates, each of which has one output and two inputs, and has one of said logic gate inputs connected to one of said outputs of said plural state cycle means and the other logic gate input coupled to said low frequency oscillator.

Claim 12

The equalizer system of claim 5 in which said maximizing circuit means also includes a plurality of up-down counters, there being one counter for each of said stages, the inputs of said counters connecting to the outputs of said gates and the outputs of said counters connecting to said equalizer.

Claim 13

The equalizer system of claim 4 in which said maximizing circuit includes: a. a sample and hold circuit having an input coupled to said quality determining means output to periodically sample the signal from said quality determining means, and having an output to produce thereon a signal which is identical to the signal which was last sampled, b. a comparator circuit having inputs coupled to the output of said sample and hold circuit and to the output of said quality determining means to compare signals on said outputs and produce a signal which corresponds to the difference between said input signals whereby the signal produced represents the increase or decrease in quality of the equalized digital information.

Claim 14

The equalizer system of claim 4 in which said source of digital infOrmation produces digital information in the form of a digitally modulated carrier, said quality determining means includes a demodulator having an input connected to said output of said equalizer for demodulating the carrier to obtain a digital signal, and said quality determining means also includes a quality determinator having an input connected to the output of said demodulator and an output connected to said maximizing circuit means.

Claim 15

A digital adaptive frequency domain equalizer system which comprises: a. a source of digital information, b. an electronically controllable frequency domain equalizer having an input coupled to said source and having a digital information output and having a plurality of sections and which includes in each said section:

Claim 16

A digital adaptive frequency domain equalizer system which comprises: a. a source of digital information, b. an electronically controllable frequency domain equalizer having an input coupled to said source and having a digital information output and having a plurality of sections and which includes in each said section:

Claim 17

The equalizer system of claim 9 in which said source of digital information produces digital information in the form of a digitally modulated carrier, said quality determining means includes a demodulator having an input connected to said output of said equalizer for demodulating the carrier to obtain a digital signal, and said quality determining means also includes a quality determinator having an input connected to the output of said demodulator and an output connected to said maximizing circuit means.

Claim 18

The equalizer system to claim 10 in which said maximizing circuit includes: a. a sample and hold circuit having an input coupled to said quality determining means output to periodically sample the signal from said quality determining means, and having an output to produce thereon a signal which is identical to the signal which was last sampled, b. a comparator circuit having inputs coupled to the output of said sample and hold circuit and to the output of said quality determining means to compare signals on said outputs and produce a signal which corresponds to the difference between said input signals whereby a signal is produced which represents the increase or decrease in quality of the equalized digital information.