US3746882A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input synchronizer circuit
Assignee: Boeing North American Inc
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Filing: 1971-07-02
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Granted: 1973-07-17
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Expires: 1991-07-02
Abstract
Abstract A field effect transistor is turned on by a clock signal for sampling an input signal. A voltage level representing the input signal is processed through the synchronizer circuit and appears at the output. A signal representing the inverted output is fed back through a logic gate which also receives the clock signal. The feedback signal holds the output in a good logic state until the input is changed during a subsequent sampling time.
Inventors
- 👤 G Heimbigner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
372 words
A synchronizer circuit comprising, a plurality of field effect transistors, each of said field effect transistors having a conduction path between a source electrode and a drain electrode, each of said field effect transistors having a gate electrode for controlling conduction through said conduction path, first source means for supplying a first voltage level, second source means for supplying a second voltage level, first, second and third field effect transistors having the conduction paths thereof connected in electrical series between said first and second source means in order to receive the respective voltage levels, first means providing a data input signal to the control electrode of the second field effect transistor, fourth, fifth and sixth field effect transistors having the conduction paths thereof connected in electrical series between said first and second source means in order to receive the respective voltage levels, second means providing a data sampling signal to the control electrode of each of said first and fourth field effect transistors, the control electrode of said fifth field effect transistor connected at a common point of the conduction paths of said second and third field effect transistors, a first output terminal connected to a common point of the conduction paths of said fifth and sixth field effect transistors to produce an output signal, a seventh field effect transistor having the conduction path thereof connected in electrical parallel with the conduction path of said fourth field effect transistor, eighth and ninth field effect transistors having the conduction paths thereof connected in electrical series between said first and second source means in order to receive the respective voltage levels, the control electrode of said eighth field effect transistor connected to a common point of the conduction paths of said fifth and sixth field effect transistOrs, a second output terminal connected to a common point of the conduction paths of said eighth and ninth field effect transistors to produce an inverted output signal relative to the output signal at said first output terminal, the control electrode of said seventh field effect transistor connected to said second output terminal to receive said inverted output signal, and third means providing control signals to the control electrode of said third, sixth and ninth field effect transistors.
Claim 2
Dependent Claim
372 words
A synchronizer circuit comprising, a plurality of field effect transistors, each of said field effect transistors having a conduction path between a source electrode and a drain electrode, each of said field effect transistors having a gate electrode for controlling conduction through said conduction path, first source means for supplying a first voltage level, second source means for supplying a second voltage level, first, second and third field effect transistors having the conduction paths thereof connected in electrical series between said first and second source means in order to receive the respective voltage levels, first means providing a data input signal to the control electrode of the second field effect transistor, fourth, fifth and sixth field effect transistors having the conduction paths thereof connected in electrical series between said first and second source means in order to receive the respective voltage levels, second means providing a data sampling signal to the control electrode of each of said first and fourth field effect transistors, the control electrode of said fifth field effect transistor connected at a common point of the conduction paths of said second and third field effect transistors, a first output terminal connected to a common point of the conduction paths of said fifth and sixth field effect transistors to produce an output signal, a seventh field effect transistor having the conduction path thereof connected in electrical parallel with the conduction path of said fourth field effect transistor, eighth and ninth field effect transistors having the conduction paths thereof connected in electrical series between said first and second source means in order to receive the respective voltage levels, the control electrode of said eighth field effect transistor connected to a common point of the conduction paths of said fifth and sixth field effect transistOrs, a second output terminal connected to a common point of the conduction paths of said eighth and ninth field effect transistors to produce an inverted output signal relative to the output signal at said first output terminal, the control electrode of said seventh field effect transistor connected to said second output terminal to receive said inverted output signal, and third means providing control signals to the control electrode of said third, sixth and ninth field effect transistors.
Claim 3
Dependent Claim
34 words
The synchronizer circuit recited in claim 1 wherein said second means provides a data sampling signal of the same phase to the control electrode of each of said first and fourth field effect transistors.
Claim 4
Dependent Claim
30 words
The synchronizer circuit recited in claim 1 wherein said third means is connected to receive one of said first and second voltage levels from the first or second source means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-16 | 1977-01-15 | 1977-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-16 | 1981-01-15 | 1981-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-16 | 1985-01-15 | 1985-07-17 | $7700.00 | Window Closed / Lapsed |