Hybrid circuit arrangement with metal oxide varistor shunt

Claim 2

The combination according to claim 1 in which said first electronic circuit means is a resistor.

Claim 3

The combination according to claim 1 in which said first electronic circuit means is a capacitor.

Claim 4

The combination according to claim 1 in which said first electronic circuit means is an inductance means.

Claim 5

The combination according to claim 1 in which the spacing between said electrical conductors at their interconnection with said metal oxide varistor body means is less than the thickness of said varistor body means normal to said spacing.

Claim 6

The combination according to claim 1 in which dielectric means is attached to said metal oxide varistor body means between its interconnections with said electrical conductors.

Claim 7

The combination comprising a substrate having first and second opposed major surfaces comprised of a metal oxide varistor body lying along at least said first major surface and having an alpha in excess of 10 in the current density range of from 10 3 to 102 amperes per square centimeter, first and second electrical conductors each having first and second major surfaces, said first major surfaces of said conductors lying in ohmic contact with said first major surface of said substrate, and said electrical conductors being laterally spaced to form a conduction gap therebetween along said first major surface, and discrete electronic circuit means lying in conductive contact with each of said first and second electrical conductors along said second major surfaces thereof.

Claim 8

The combination according to claim 8 in which said discrete electronic circuit means is a semiconductive element.

Claim 9

The combination according to claim 8 in which said discrete electronic circuit means is a capacitor.

Claim 10

The combination according to claim 8 in which said discrete electronic circuit means is a resistor.

Claim 11

The combination according to claim 8 in which said discrete electronic circuit means is an inductance means.

Claim 12

The combination according to claim 8 in which said varistor body lies along both said first and second opposed major surfaces of said substrate and additionally including a third electrical conductor lying In ohmic contact with said second major substrate surface, the thickness of said varistor body being greater than the width of the conduction gap.

Claim 13

The combination according to claim 8 in which said varistor body extends between said first and second opposed major surface of said substrate and exhibits a thermal conductivity of at least 0.01 calorie-cm/sec-cm2-*C and additionally including heat sink means lying in thermally conductive relation with said second major surface.

Claim 14

The combination according to claim 8 additionally including a third electrode associated with said first major substrate surface separated from said first electrical conductor by said second electrical conductor, said third electrical conductor being laterally spaced from said second electrical conductor by a second conduction gap width which exceeds the width of the conduction gap width between said first and second electrical conductors.

Claim 15

The combination according to claim 8 in which said substrate is additionally comprised of a dielectric support associated with said varistor body.

Claim 16

The combination according to claim 16 in which a portion of said dielectric support lies along said first major surface.

Claim 17

The combination according to claim 16 in which a portion of said dielectric support lies along said first major substrate surface and in contact with said first and second electrical conductors.

Claim 18

The combination comprising first and second laterally spaced electrical conductors, a semiconductive substrate lying in conductive contact with said first and second spaced electrical conductors for conducting current therebetween when an electrical potential less than a predetermined maximum value is impressed across said electrical conductors, and metal oxide varistor body means having an alpha in excess of 10 in the current density range of from 10 3 to 102 amperes per square centimeter lying in conductive contact with and being supported by said first and second electrical conductors for variably conducting current therebetween in shunt with said semiconductive substrate to maintain the electrical potential impressed across said electrical conductors less than the predetermined maximum value.

Claim 19

The combination according to claim 19 in which said varistor body means is provided with a dielectric coating between its interconnections with said electrical conductors.

Claim 20

The combination according to claim 19 in which said varistor body means is provided with a glass coating between its interconnections with said electrical conductors.

Claim 21

The combination according to claim 19 in which said varistor body means is interconnected with said first and second electrical conductors along an edge surface.

Claim 22

The combination according to claim 19 in which said varistor body means is interconnected with said first and second electrical conductors along an edge surface and is tranversely oriented with respect to said semiconductive substrate.

Claim 23

The combination according to claim 19 in which said semiconductive substrate is provided with a junction interposed between its interconnections with said first and second electrical conductors, said junction having a maximum reverse voltage blocking capability dictating the predetermined maximum potential.

Claim 24

The combination according to claim 19 in which said semiconductive element is a monolithic integrated circuit.