US3743858A
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Shift register
Assignee: Bombardier Transportation Holdings USA Inc
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Filing: 1971-10-04
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Granted: 1973-07-03
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Expires: 1991-10-04
Abstract
Abstract A shift register is comprised of a plurality of bistable devices with the output of a given bistable device being coupled to the input of the following bistable device by way of a memory circuit which stores a signal indicative of the binary state of the given bistable device in response to the concurrent provision of a shift signal. A reset pulse for each stage of the shift register is also provided in response to the provision of the shift signal. The memory device stores the binary signal for a predetermined interval of time after the cessation of the reset signal, so that the following bistable device may be set to the same binary state that the given bistable device was in prior to the provision of the reset signal.
Inventors
- 👤 D Woods
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:27
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; G; G06; G06F; G06F1/00; G06F1/02
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
411 words
In a shift register having n stages, where n is an integer, the combination comprising: signal generating means for providing a shift pulse at a frequency f1 and a load pulse at a frequency f2 f1/n, said load pulse being applied to the first stage of said shift register; n-1 memory means having first and second inputs and an output, the output of the first stage of said shift register being connected to the first input of the first memory means, and the output of the first memory means being connected to the input of the second stage of said shift register and so on, with the output of the nth-1 stage of said shift register being connected to the first input of the nth memory means, and the output of the nth-1 memory means being connected to the input of the nth stage of said shift register, the second input of each memory means being responsive to said shift pulse for providing a set pulse at the output of a given memory means whenever the first input of the given memory means is concurrently at a predetermined binary level; wherein each of said n-1 memory means comprises first and second transistors having their conduction paths connected in series by way of the primary winding of a transformer, the control electrode of the first transistor comprising the first input of said memory means and the control electrode of the second transistor comprising the second input of said memory means, the secondary winding of said transformer being connected to the control electrode of a third transistor, the output electrode of said third transistor comprising the output of said memory means; a pulse shaping network responsive to said shift pulse for providing a reset pulse to each stage of said shift register, said reset pulse having a leading edge substantialLy in time coincidence with the leading edge of said set pulse with said set pulse having a width greather than the width of said reset pulse; and a plurality of AND gates coupled to the outputs of the respective stages of said shift register, said AND gates each having a signal input, a control input and an output at which a periodic signal is provided only so long as a periodic signal is provided at the signal input concurrent with a selected binary level at a predetermined frequency being applied to the control input from the output of a selected shift register stage.
Claim 2
Dependent Claim
411 words
In a shift register having n stages, where n is an integer, the combination comprising: signal generating means for providing a shift pulse at a frequency f1 and a load pulse at a frequency f2 f1/n, said load pulse being applied to the first stage of said shift register; n-1 memory means having first and second inputs and an output, the output of the first stage of said shift register being connected to the first input of the first memory means, and the output of the first memory means being connected to the input of the second stage of said shift register and so on, with the output of the nth-1 stage of said shift register being connected to the first input of the nth memory means, and the output of the nth-1 memory means being connected to the input of the nth stage of said shift register, the second input of each memory means being responsive to said shift pulse for providing a set pulse at the output of a given memory means whenever the first input of the given memory means is concurrently at a predetermined binary level; wherein each of said n-1 memory means comprises first and second transistors having their conduction paths connected in series by way of the primary winding of a transformer, the control electrode of the first transistor comprising the first input of said memory means and the control electrode of the second transistor comprising the second input of said memory means, the secondary winding of said transformer being connected to the control electrode of a third transistor, the output electrode of said third transistor comprising the output of said memory means; a pulse shaping network responsive to said shift pulse for providing a reset pulse to each stage of said shift register, said reset pulse having a leading edge substantialLy in time coincidence with the leading edge of said set pulse with said set pulse having a width greather than the width of said reset pulse; and a plurality of AND gates coupled to the outputs of the respective stages of said shift register, said AND gates each having a signal input, a control input and an output at which a periodic signal is provided only so long as a periodic signal is provided at the signal input concurrent with a selected binary level at a predetermined frequency being applied to the control input from the output of a selected shift register stage.
Claim 3
Dependent Claim
66 words
The combination claimed in claim 1, wherein said pulse shaping network comprises a transistor having its control electrode connected to said signal generating means for receiving said shift pulse, and having the primary winding of a transformer connected in series with the conduction path of said transistor, the secondary winding of said transformer being connected to the reset connection of each stage of said shift register.
Claim 4
Dependent Claim
335 words
In a shift register having n stages, where n is an integer, the combination comprising: signal generating means for providing a shift pulse at a frequency f1 and a load pulse at a frequency f2 f1/n, said load pulse being applied to the first stage of said shift register; n-1 memory means each having first and second inputs and an output, the output of the first stage of said shift register being connected to the first input of the first memory means, and the output of the first memory means being connected to the input of the second stage of said shift register and so on, with the output of the nth-1 stage of said shift register being connected to the first input of the nth memory means, and the output of the nth-1 memory means being connected to the input of the nth stage of said shift register, the second input of each memory means being responsive to said shift pulse for providing a set pulse at the output of a given memory means wherever the first input of the given memory is concurrently at a predetermined binary level; wherein each of said n-1 memory means comprises first and second transistors having their conduction paths connected in series by way of the primary winding of a transformer, the control electrode of the first transistor comprising the first input of said memory means and the control electrode of the second transistor comprising the second input of said memory means, the secondary winding of said transformer being connected to the control electrode of a third transistor, the output electrode of said third transistor comprising the output of said memory means; and a pulse shaping network responsive to said shift pulse for providing a reset pulse to each stage of said shift register, said reset pulse having a leading edge substantially in time coincidence with the leading edge of said set pulse with said set pulse having a width greater than the width of said reset pulse.
Claim 5
Dependent Claim
335 words
In a shift register having n stages, where n is an integer, the combination comprising: signal generating means for providing a shift pulse at a frequency f1 and a load pulse at a frequency f2 f1/n, said load pulse being applied to the first stage of said shift register; n-1 memory means each having first and second inputs and an output, the output of the first stage of said shift register being connected to the first input of the first memory means, and the output of the first memory means being connected to the input of the second stage of said shift register and so on, with the output of the nth-1 stage of said shift register being connected to the first input of the nth memory means, and the output of the nth-1 memory means being connected to the input of the nth stage of said shift register, the second input of each memory means being responsive to said shift pulse for providing a set pulse at the output of a given memory means wherever the first input of the given memory is concurrently at a predetermined binary level; wherein each of said n-1 memory means comprises first and second transistors having their conduction paths connected in series by way of the primary winding of a transformer, the control electrode of the first transistor comprising the first input of said memory means and the control electrode of the second transistor comprising the second input of said memory means, the secondary winding of said transformer being connected to the control electrode of a third transistor, the output electrode of said third transistor comprising the output of said memory means; and a pulse shaping network responsive to said shift pulse for providing a reset pulse to each stage of said shift register, said reset pulse having a leading edge substantially in time coincidence with the leading edge of said set pulse with said set pulse having a width greater than the width of said reset pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-02 | 1977-01-01 | 1977-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-02 | 1981-01-01 | 1981-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-02 | 1985-01-01 | 1985-07-03 | $7700.00 | Window Closed / Lapsed |