US3743856A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Exclusive-or ecl logic circuit
Assignee: Signetics Corp
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Filing: 1971-07-06
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Granted: 1973-07-03
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Expires: 1991-07-06
Abstract
Abstract An Exclusive OR circuit for emitter coupled logic (ECL) arrays having two differential current switches with their respective collectors either cross coupled to provide an inverted Exclusive OR output from a negative logic convention.
Inventors
- 👤 D Leuthold
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/212
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
163 words
An Exclusive OR logic circuit of the emitter coupled logic type having an output signal, F, and input signals A and B said output signal being related to said input signals by F AB + A B * A + B said circuit comprising: first and second differential but non-saturating current switches each having a first transistor for respectively receiving said A and B signals and a second transistor for receiving a reference signal the bases of said second transistors being coupled together to receive said reference signal and the emitters of said first and second transistors being tied together for each switch; first and second current sink means coupled respectively to said tied emitters of said first and second switches; means for cross-coupling the collectors of said first and second transistors of said first switch respectively to collectors of said second and first transistors of said second switch; and means for tieing said coupled collectors together to provide said output signal, F.
Claim 2
Dependent Claim
163 words
An Exclusive OR logic circuit of the emitter coupled logic type having an output signal, F, and input signals A and B said output signal being related to said input signals by F AB + A B * A + B said circuit comprising: first and second differential but non-saturating current switches each having a first transistor for respectively receiving said A and B signals and a second transistor for receiving a reference signal the bases of said second transistors being coupled together to receive said reference signal and the emitters of said first and second transistors being tied together for each switch; first and second current sink means coupled respectively to said tied emitters of said first and second switches; means for cross-coupling the collectors of said first and second transistors of said first switch respectively to collectors of said second and first transistors of said second switch; and means for tieing said coupled collectors together to provide said output signal, F.
Claim 3
Dependent Claim
14 words
A circuit as in claim 1 where said tieing means include emitter-follower connected transistors.
Claim 4
Dependent Claim
15 words
A circuit as in claim 1 together with enable means to provide an unconditional output.
Claim 5
Dependent Claim
28 words
A circuit as in claim 3 where said enable means includes first and second transistors respectively parallel connected to said first transistors of said first and second switches.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-02 | 1977-01-01 | 1977-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-02 | 1981-01-01 | 1981-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-02 | 1985-01-01 | 1985-07-03 | $7700.00 | Window Closed / Lapsed |