Busy bit for time division multiplex signals to reduce signal processing time

Claim 2

In a time division multiplex switching network including switchable space-divided signal paths for time division multiplex data signals and control memories for controlling the operation of switching equipment to effect different space-divided data signal path connections through said network in different byte times of a time division multiplex signal frame, means for examining the binary code signal state of a predetermined bit in each signal byte time of a time division multiplex signal in one of said paths, switching means comprising a unit of said switching equipment and connected in said one path for controllably determining path configuration in each byte time, and means, including said control memories and responsive to the state of said predetermined bit, for controlling the condition of said switching means during each byte time including such predetermined bit.

Claim 3

The network in accordance with claim 1 in which said controlling means comprises means for storing switch control signals in a recirculating storage loop, means for applying said switch control signals to operate said switching means, and means responsive to said predetermined bit for controlling recirculation in said loop.

Claim 4

The network in accordance with claim 1 in which there are provided means for interacting said predetermined bit with signal contents of said control memories corresponding to the byte of said predetermined bit, and means for erasing said contents of said control memories controlling said switching means in response to a first predetermined state of said predetermined bit.

Claim 5

The network in accordance with claim 3 in which said control memories comprise a plurality of shift registers, each having an output coupled for controlling different ones of said switching means, means for controllably recirculating control signals in said shift registers, a buffer register connected to supply signals to control said recirculating means, further shift register, and means for coupling the contents of the last mentioned shift register in bit parallel to said buffer register at the end of each signal frame, and means for coupling said predetermined bit from each said signal byte into said last-mentioned shift register at the byte recurrence rate of said time division multiplex signal.

Claim 6

The network in accordance with claim 1 in which said network is a multistage switching network and said switching equipment comprises a plurality of said switching equipment units operated in selectable byte times by output signals from said control memories, and said controlling means comprises a plurality of control memory units each individually coupled for controlling a different one of said equipment units, means for comparing corresponding ones of said predetermined bits for circuits to be interconnected in a common byte time and for producing, in such byte time, signal state match or mismatch indications as a function of signal states of such bits, and means responsive to said match indication for writing into an appropriate one of said memory units a signal for controlling the coupled equipment unit.

Claim 7

The network in accordance with claim 1 in which at least a portion of each signal path through said network includes a magnetic single-wall domain shift register path, said controlling means comprises at least one control memory unit coupled to said part of said path, said control memory unit including magnetic single-wall domain shift register means, said control memory unit further includes means for injecting magnetic domains into said one data signal path, and means, responsive to coincidence of domains in said signal path and in said control memory unit, are provided for diverting said signal path domain into said control memory unit.

Claim 8

The network in accordance with claim 1 in which said switching means comprises a multistage switching network for interconnecting signal transmission circuits by way of switching equipment units operated in selectable byte times by output signals from said control memories, and at least one of said stages comprises means for overwriting said predetermined bits in a predetermined proportion of said byte times with a signal indicating that the corresponding byte time is in use whether or not such byte time is actually in use.

Claim 9

A time division multiplex signal communication system comprising a plurality of input signal paths, a plurality of output signal paths, means for selectively coupling said input signal paths to different ones of said output signal paths in successive signal time slots so that a signal from an input path is steered to one of said output paths as a function of the configuration of said coupling means in the time slot of such signal, means for forming signals on said inpUt paths into successive time slots of recurrent time frames, time slot signals being grouped into signal bit groups of at least two signal bits, one of which is a busy-bit signal and is allocated for a binary coded signal indicating whether or not the corresponding time slot is in use, means for writing the signal state of said busy bit to indicate whether or not the corresponding time slot is in use, and means, responsive to said state of said busy bit, for determining said coupling means configuration for such time slot.

Claim 10

A time division multiplex signal communication system comprising a plurality of input signal paths, a plurality of output signal paths, means for selectively coupling said input signal paths to different ones of said output signal paths in successive signal time slots so that a signal from an input path is steered to one of said output paths as a function of the configuration of said coupling means in the time slot of such signal, means for forming signals on said inpUt paths into successive time slots of recurrent time frames, time slot signals being grouped into signal bit groups of at least two signal bits, one of which is a busy-bit signal and is allocated for a binary coded signal indicating whether or not the corresponding time slot is in use, means for writing the signal state of said busy bit to indicate whether or not the corresponding time slot is in use, and means, responsive to said state of said busy bit, for determining said coupling means configuration for such time slot.

Claim 11

The system in accordance with claim 8 in which said selective coupling means comprises means for overwriting a predetermined proportion of all of said busy bit intervals with a signal indicating that the corresponding time slot is in use whether or not such time slot is actually in use.

Claim 12

In combination, a time division multiplex signal communication network having selectable space-divided signal paths for coupling time division multiplex information signals through such network, means for storing a control signal pattern, said storing means comprising a recirculating loop storage means for said pattern, means for coupling said control signal pattern to said network for controlling selection of one of said paths in a time slot in each frame of said time division multiplx signals, and means, responsive to a first or a second signal state of a predetermined signal bit in each time slot of an information signal in said one path, for enabling recirculation of said pattern in said loop storage means upon occurrence of said first state and blocking recirculation on occurrence of said second state.

Claim 13

In combination, a time division multiplex signal communication network having selectable space-divided signal paths for coupling time division multiplex information signals through such network, means for storing a control signal pattern, said storing means comprising a recirculating loop storage means for said pattern, means for coupling said control signal pattern to said network for controlling selection of one of said paths in a time slot in each frame of said time division multiplx signals, and means, responsive to a first or a second signal state of a predetermined signal bit in each time slot of an information signal in said one path, for enabling recirculation of said pattern in said loop storage means upon occurrence of said first state and blocking recirculation on occurrence of said second state.

Claim 14

The combination in accordance with claim 10 in which said controlling means comprises first means for coupling said control signal pattern from said loop into said one path, and second means for coupling said predetermined bit from said one path into said loop, in response to passage of said pattern through said first coupling means, for replacing said pattern in said loop.

Claim 15

The combination in accordance with claim 10 in which said controlling means comprises gating means connected in series in said loop, and means, responsive to said predetermined bit first state, for enabling said gating means to recirculate said pattern in each signal frame in which such state occurs.

Claim 16

The combination in accordance with claim 1 in which said switching means comprises a plurality of switching equipment units in a stage of said network, and said controlling means comprises a plurality of control memory units coupled for controlling respective ones of said equipment units, a shift register adapted for operation at the recurrence rate of byte times in said time division signals, means for inserting into said register a signal indicating the start of one of said frames, means for generating a logic signal indicating one of said control memory units, gating means for controllably coupling outputs of respective stages of said register to different ones of said control memory units, and means for applying said logic signal to said gating means for coupling said frame start signal from said register to one of said control memory units for enabling operation of such unit for controlling coupling of time division multiplex signals through said equipment units.

Claim 17

The network in accordance with claim 1 in which said switching means comprises a plurality of switching equipment units in a stage of said network, each unit corresponding to a different byte time of an input signal frame of the stage, and said controlling means comprises means for matching said predetermined bits of an input path to said stage and an output path from said stage to produce a match signal indication in a byte time when the predetermined bits have a predetermined signal state, the last-mentioned byte time corresponding to one of said units, means for providing to all of said unIts time coded signals for indicating when said one unit is to be operated, and means for enabling only said one unit to respond to said time coded signals.

Claim 18

The network in accordance with claim 14 in which said matching means comprises means for sequentially sampling said predetermined bit in each byte time of a time division multiplex signal frame of said input path, means for sequentially sampling said predetermined bit in each byte time of a time division multiplex signal frame of said output path, and means for comparing outputs of said input path sampling means and output path sampling means to produce said match signal indication.

Claim 19

The network in accordance with claim 14 in which said matching means comprises means for simultaneously sampling said predetermined bits in each byte time of a time division multiplex signal frame of said input path, means for simultaneously sampling said predetermined bits in each byte time of a time division multiplex signal frame of said output path, a coincidence gate for producing said match signal indication in response to a coincidence of inputs in a predetermined signal state, and means for sequentially applying corresponding byte time samples from said input path sampling means and output path sampling means to different inputs of said coincidence gate.

Claim 20

The combination in accordance with claim 16 in which said simultaneous sampling means each comprise plural gating means, each connected to receive at an input thereof data signals from a different one of said units, and means for enabling said gating means in said predetermined bit time of a byte time in one of said data signal paths, and said sequential applying means comprises for each of said simultaneous sampling means a buffer register connected for receiving outputs of said gating means, a shift register, plural gating means, each connected to couple signals from a different stage of said buffer register to a corresponding stage of said shift register, means for actuating the last-mentioned gating means after said predetermined bit time of a byte time in said one data signal path, and means for coupling output from said shift register to said coincidence gate.

Claim 21

The network in accordance with claim 5 in which each stage of said network includes a plurality of input paths, a plurality of output paths, and a plurality of said equipment units for coupling said input paths to said output paths, and said comparing means comprises means for sequentially sampling said predetermined bit in each byte time of a time division multiplex signal frame of one of said input paths, means for sequentially sampling said predetermined bit in each byte time of a time division multiplex signal frame of one of said output paths, and means for matching outputs of said input path sampling means and output path sampling means to produce said signal indications.

Claim 22

The network in accordance with claim 5 in which each stage of said network includes a plurality of input paths, a plurality of output paths, and a plurality of said equipment units for coupling said input paths to said output paths, and said comparing means comprises means for simultaneously sampling said predetermined bits in each byte time of a time division multiplex signal frame of one of said input paths, means for simultaneously sampling said predetermined bits in each byte time of a time division multiplex signal frame of one of said output paths, a coincidence gate for producing said match signal indication in response to a coincidence of inputs in a predetermined signal state, and means for sequentially applying corresponding byte time samples from said input path sampling means and output path sampling means to different inputs of said coincidence gate.

Claim 23

The network in accordance with claim 14 in which said enabling means comprises for each stage of said network a shift registEr and means for operating said register at a byte time clock rate corresponding to the number of said units in such network stage, means for entering a frame-start signal into said shift register, gating means for coupling each stage of said shift register to a corresponding one of said units of such network stage for enabling such one unit, and means for providing to said gating means in a time slot corresponding to said one unit a signal for enabling all of said gating means for such network stage.