Data processing method and apparatus adapted to sequentially pack error correcting characters into memory locations

Claim 2

A data processing system comprising a memory having a plurality of storage locations; means for sequentially receiving a plurality of information items to be stored into the memory, each information item including a word and an associated character; means for storing each received information item into the memory, the storing means including means for selecting a different one of a first plurality of the storage locations for storing each of a sequence of received words and including means for sequentially selecting the same one of a second plurality of storage locations for storing a plurality of sequentially received characters respectively associated with the plurality of words stored in the first plurality of storage locations so as to pack such characters together in the same storage location.

Claim 3

A data processing system according to claim 1 comprising a source for providing addresses, the storing means including means responsive to a memory address for accessing a storage location, circuitry for converting a plurality of provided addresses to the same memory address, and means for providing to the accessing means said same address for identifying the actual storage location for storing the associated characters.

Claim 4

A data processing system according to claim 1 comprising means operative for reading out a word form one storage location and its associated character from said same storage location.

Claim 5

A data processing system according to claim 1 wherein the memory comprises a plurality of addressable modules each having a plurality of addressable locations, means enabling substantially simultaneous access to a pair of said modules causing access to a location in one module for a memory word and causing access to a location in the other module for the word and associated character.

Claim 6

A data processing system according to claim 1 further including means for selectively providiNg a packing disable signal, and the selecting means being responsive the packing disable signal to select storage locations in said second plurality for storing words so as to make more storage locations available for storing memory words.

Claim 7

A digital data processing system comprising: a memory system having a plurality of memory locations, each location for storing a binary coded word or a plurality of binary coded error correcting characters; means for correcting an erroneous word in accordance with an error correcting character; means for sequentially receiving a plurality of words and, in association with each word, an error correcting character; means for accessing the memory system including means for sequentially storing a plurality of said received characters in one of said memory locations and for storing each received word in a different memory location from its associated character, means for retrieving from said memory system a word stored in a memory location thereof and the associated error correcting character from a different memory location; and means for providing the retrieved word and character to said correcting means.

Claim 8

A digital data processing system comprising: a memory system having a plurality of memory locations, each location for storing a binary coded word or a plurality of binary coded error correcting characters; means for correcting an erroneous word in accordance with an error correcting character; means for sequentially receiving a plurality of words and, in association with each word, an error correcting character; means for accessing the memory system including means for sequentially storing a plurality of said received characters in one of said memory locations and for storing each received word in a different memory location from its associated character, means for retrieving from said memory system a word stored in a memory location thereof and the associated error correcting character from a different memory location; and means for providing the retrieved word and character to said correcting means.

Claim 9

A digital data processing system according to claim 6 wherein said memory system comprises a plurality of memory modules accessible substantially in parallel, said means for storing comprising means for storing a word in one memory module and its associated error correcting character in another memory module substantially in parallel, said retrieving means comprising means for retrieving a word from one memory module and its associated error correcting character from another memory module substantially in parallel.

Claim 10

A system according to claim 6 wherein the memory system includes means responsive to a memory address for selecting a memory location; and the means for accessing includes a source for providing addresses, circuitry responsive to each provided address for supplying to the memory system a memory address for a word and a memory address for an associated character.

Claim 11

A system according to claim 8 wherein the memory system comprises a plurality of addressable memory modules accessible substantially in parallel; and the circuitry for supplying memory addresses includes means for supplying a memory address to one memory module for selecting a location for a word and for supplying a memory address to a different memory module for a character.

Claim 12

In a data processing system, the combination comprising a memory having a plurality of addressable memory locations each having a predetermined number of bit cells, register means coupled to the memory for sequentially transferring words therebetween; means for producing associated error correcting characters for words to be stored in memory, means for correcting an erroneous word read from the memory in accordance with an error correcting character read from the memory; and memory accessing means for selecting and for writing into and reading from mutually exclusive locations of the memory words and the error correcting characters, the memory accessing means including means for sequentially selecting mutually exclusive subsets of the bit cells of one location for storing a plurality of error correcting characters.

Claim 13

In a data processing system, the combination comprising a memory having a plurality of addressable memory locations each having a predetermined number of bit cells, register means coupled to the memory for sequentially transferring words therebetween; means for producing associated error correcting characters for words to be stored in memory, means for correcting an erroneous word read from the memory in accordance with an error correcting character read from the memory; and memory accessing means for selecting and for writing into and reading from mutually exclusive locations of the memory words and the error correcting characters, the memory accessing means including means for sequentially selecting mutually exclusive subsets of the bit cells of one location for storing a plurality of error correcting characters.

Claim 14

The combination according to claim 10 wherein the memory comprises a plurality of independently operating memory modules and wherein the means for selecting memory locations includes means for simultaneously selecting a memory location for a word and a memory location for an error correcting character.

Claim 15

A digital data processing system comprising: a memory system comprising a plurality of independently addressable memory modules each having addressable memory locations, each location for storing a binary coded word or a plurality of binary coded error correcting characters; means for correcting an erroneous word in accordance with an error correcting character; means for providing one of said words aNd, associated therewith, an error correcting character; means for providing a first address; means for converting said first address to second and third addresses for identifying respectively a memory location in one memory module for said provided word and a memory location in a different memory module for said provided associated error correcting character, said converting means forming the same third address for a plurality of different first addresses; means for storing one of said provided words and an associated error correcting character in said memory system and comprising means for storing such word in a memory location identified by one of said second addresses and means for storing such associated error correcting character in a memory location identified by said third address; and means for reading a desired word and associated error correcting character from said memory system comprising means for reading out such desired word from the memory location identified by one of said second addresses and means for reading out such associated error correcting character from the memory location identified by one of said third addresses.

Claim 16

A digital data processing system comprising: a memory system comprising a plurality of independently addressable memory modules each having addressable memory locations, each location for storing a binary coded word or a plurality of binary coded error correcting characters; means for correcting an erroneous word in accordance with an error correcting character; means for providing one of said words aNd, associated therewith, an error correcting character; means for providing a first address; means for converting said first address to second and third addresses for identifying respectively a memory location in one memory module for said provided word and a memory location in a different memory module for said provided associated error correcting character, said converting means forming the same third address for a plurality of different first addresses; means for storing one of said provided words and an associated error correcting character in said memory system and comprising means for storing such word in a memory location identified by one of said second addresses and means for storing such associated error correcting character in a memory location identified by said third address; and means for reading a desired word and associated error correcting character from said memory system comprising means for reading out such desired word from the memory location identified by one of said second addresses and means for reading out such associated error correcting character from the memory location identified by one of said third addresses.

Claim 19

The method as defined in claim 13 additionally comprising the steps of producing an indication of a subset of bit cells and controlling the writing of the character so that the character is written into the indicated subset.

Claim 20

A data processing system comprising a memory having a plurality of storage locations, means for sequentially receiving a plurality of words and associated with each word a character, means for associating certain of said storage locations together and means responsive to said associating means for packing together one at a time in a common storage location a plurality of said received characters and for storing said received words associated with each said packed character in other storage locations associated with said common storage location.

Claim 21

A data processing system comprising a memory having a plurality of storage locations, means for sequentially receiving a plurality of words and associated with each word a character, means for associating certain of said storage locations together and means responsive to said associating means for packing together one at a time in a common storage location a plurality of said received characters and for storing said received words associated with each said packed character in other storage locations associated with said common storage location.

Claim 22

A data processing system according to claim 15 comprising means responsive to said associating means for reading out a word and its associated character from associated memory locations.

Claim 23

A data processing system according to claim 16 wherein said associating means comprises means for identifying one of a plurality of character positions in a common storage location, said packing means and reading means being responsive to said identification for respectively storing and reading in said identified storage location.

Claim 24

A data processing system according to claim 16 wherein there are a plurality of said common storage locations, each for storing a plurality of said characters, separated by a plurality of storage locations each for storing one of said words associated with one of said stored characters and said associating means is operative for associating each of said common storage locations with a separating storage location for each character stored in a common storage location.