US3742368A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse generator using schottky effect transistors
Assignee: Signetics Corp
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Filing: 1972-04-24
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Granted: 1973-06-26
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Expires: 1992-04-24
Abstract
Abstract A pulse generating circuit which produces a single output pulse in response to a step signal change at its input. The circuit includes first, second and third transistors with the first and third transistors having commonly connected outputs. The first transistor is driven by the input signal and it in turn drives the second transistor which in turn drives the third transistor. In accordance with one embodiment the first and third transistors having commonly connected outputs are Schottky effect transistors having a very small turn off delay compared to the turn off delay of the second transistor. The first and second transistors are normally on so that the output terminal is low. The third transistor is normally off. In response to a step signal change at the input of the first transistor, the first transistor goes off. Since the second transistor is a slow turn off device compared to the first and third transistors, the third transistor also stays off for a time. With both the first and third transistors off the output terminal goes high. After a period equal to the turn off delay of the second transistor, however, the second transistor turns off which turns on the third transistor, thus causing the output terminal to again go low. The duration of this pulse at the output terminal is proportional to the turn off delay of the second transistor.
Inventors
- 👤 A Gelabert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:33
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
270 words
In a circuit including a reference potential terminal, an input terminal and an output terminal, pulse generating means for generating a puLse at the output terminal in response to a step signal change at the input terminal comprising first, second and third transistors each having a base input electrode and collector and emitter output electrodes and capable of switching between on and off conditions, means for applying a bias voltage to said first, second and third transistors, the input base electrode of said first transistor coupled to the input terminal, one of said output collector and emitter electrodes of each of said first and third transistors coupled to the output terminal, one of said output collector and emitter electrodes of said second transistor coupled to the reference potential terminal, said other of the output collector and emitter electrodes of said first transistor coupled to said input base electrode of said second transistor and coupled through an impedance to the reference potential terminal so that the on or off condition of said second transistor follows the on or off condition of said first transistor, the other of said output collector and emitter electrodes of said third transistor coupled to the source of reference potential, the other of said output collector and emitter electrodes of said second transistor coupled to the input base electrode of said third transistor so that the on or off condition of said third transistor inversely follows the on or off condition of said second transistor, said first and third transistors being of a type having substantially less turn on and turn off delay than said second transistor.
Claim 2
Dependent Claim
270 words
In a circuit including a reference potential terminal, an input terminal and an output terminal, pulse generating means for generating a puLse at the output terminal in response to a step signal change at the input terminal comprising first, second and third transistors each having a base input electrode and collector and emitter output electrodes and capable of switching between on and off conditions, means for applying a bias voltage to said first, second and third transistors, the input base electrode of said first transistor coupled to the input terminal, one of said output collector and emitter electrodes of each of said first and third transistors coupled to the output terminal, one of said output collector and emitter electrodes of said second transistor coupled to the reference potential terminal, said other of the output collector and emitter electrodes of said first transistor coupled to said input base electrode of said second transistor and coupled through an impedance to the reference potential terminal so that the on or off condition of said second transistor follows the on or off condition of said first transistor, the other of said output collector and emitter electrodes of said third transistor coupled to the source of reference potential, the other of said output collector and emitter electrodes of said second transistor coupled to the input base electrode of said third transistor so that the on or off condition of said third transistor inversely follows the on or off condition of said second transistor, said first and third transistors being of a type having substantially less turn on and turn off delay than said second transistor.
Claim 3
Dependent Claim
18 words
Pulse generating means in accordance with claim 1 wherein said first and third transistors are Schottky effect transistors.
Claim 4
Dependent Claim
53 words
Pulse generating means in accordance with claim 1 wherein said first and third transistors are large area Schottky effect transistors and wherein said second transistor is a small area Schottky effect transistor so that said second transistor has a substantially greater turn on and turn off delay than said first and third transistors.
Claim 5
Dependent Claim
32 words
Pulse generating means in accordance with claim 3 wherein the duration of the pulse generated at the output terminal is proportional to the turn on or off delay of said second transistor.
Claim 6
Dependent Claim
188 words
In a circuit including a reference potential terminal and an input terminal and an output terminal, pulse generating means for generating a pulse at the output terminal in response to a step signal change at the input terminal comprising first, second and third transistors each having base emitter and collector electrodes, means for applying bias voltage to the collectors of said first, second and third transistors, said first transistor having its base coupled to the input terminal and its emitter coupled to the reference potential terminal, the collector of said first transistor being coupled to the output terminal, said second transistor base coupled to the emitter of said first transistor, the emitter of said second transistor also being coupled to the reference potential terminal, the collector of said second transistor being coupled to the base of said third transistor, the collector of said third transistor being coupled to the output terminal and the emitter of said third transistor being coupled to the reference potential terminal, and said first and third transistors being of a type having substantially less turn on and turn off delays than said second transistor.
Claim 7
Dependent Claim
188 words
In a circuit including a reference potential terminal and an input terminal and an output terminal, pulse generating means for generating a pulse at the output terminal in response to a step signal change at the input terminal comprising first, second and third transistors each having base emitter and collector electrodes, means for applying bias voltage to the collectors of said first, second and third transistors, said first transistor having its base coupled to the input terminal and its emitter coupled to the reference potential terminal, the collector of said first transistor being coupled to the output terminal, said second transistor base coupled to the emitter of said first transistor, the emitter of said second transistor also being coupled to the reference potential terminal, the collector of said second transistor being coupled to the base of said third transistor, the collector of said third transistor being coupled to the output terminal and the emitter of said third transistor being coupled to the reference potential terminal, and said first and third transistors being of a type having substantially less turn on and turn off delays than said second transistor.
Claim 8
Dependent Claim
18 words
Pulse generating means in accordance with claim 5 wherein said first and third transistors are Schottky effect transistors.
Claim 9
Dependent Claim
52 words
Pulse generating means in accordance with claim 5 wherein said first and third transistors are large areas Schottky effect transistors and wherein said second transistor is a small area Schottky effect transistor so that said second transistor has substantially greater turn on and turn off delay than said first and third transistors.
Claim 10
Dependent Claim
30 words
Pulse generating means in accordance with claim 7 wherein the duration of the pulse generated at the output terminal is proportional to the turn off delay of saId second transistor.
Claim 11
Dependent Claim
24 words
Pulse generating means in accordance with claim 8 including a Schottky diode connected between the collector of said third transistor and the output terminal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-25 | 1976-12-25 | 1977-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-25 | 1980-12-25 | 1981-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-25 | 1984-12-25 | 1985-06-26 | $7700.00 | Window Closed / Lapsed |